Research
FERIVer: An FPGA-assisted Emulated Framework for RTL Verification of RISC-V Processors
Abstract
FERIVer is a novel FPGA-assisted System-on-Chip framework designed to accelerate the Register Transfer Level (RTL) verification of RISC-V processors. It resolves the traditional trade-off between speed and accuracy by leveraging an embedded
Research
Virtual memory for real-time systems using hPMP
Abstract
To meet stringent automotive safety and security requirements, this work proposes hPMP, an extension to the RISC-V SPMP specification designed for real-time systems. The key innovation enables virtual address redirection for selected
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China firm develops one-nanometer thick RISC-V chip with 2D materials - Interesting Engineering
Abstract
A Chinese firm has achieved a major technological milestone by announcing the development of a RISC-V chip fabricated using advanced 2D materials. This cutting-edge processor boasts an unprecedented thickness of just one
Research
World’s first 1-nanometre RISC-V chip made in China with 2D materials - South China Morning Post
Abstract
Researchers in China have reportedly created the world's first chip operating at an unprecedented 1-nanometre scale. This radical miniaturization was achieved by utilizing advanced 2D materials, surpassing the limitations of
Research
ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions
Abstract
ARCANE introduces a novel Adaptive RISC-V Cache Architecture that transforms the traditional cache subsystem into a tightly-coupled compute-near-memory coprocessor, specifically addressing the von Neumann data movement bottleneck. This architecture allows the RISC-V
Research
Exploring energy consumption of AI frameworks on a 64-core RV64 Server CPU
Abstract
This study conducts a comprehensive energy consumption benchmark of deep learning inference models running on the 64-core SOPHON SG2042 RISC-V server CPU. The research compared leading AI frameworks, including PyTorch, ONNX Runtime,