Research
Quadrilatero: A RISC-V programmable matrix coprocessor for low-power edge applications
Abstract
Quadrilatero is an open-source RISC-V programmable matrix coprocessor designed to optimize AI workloads in low-power edge applications. It utilizes a systolic array architecture and a streamlined matrix ISA extension to overcome the
Research
Just TestIt! An SBST Approach To Automate System-Integration Testing
Abstract
This paper introduces TestIt, an open-source Python package designed to automate full-system integration testing using a Software-Based Self-Test (SBST) approach. TestIt dynamically generates test vectors and golden references, significantly reducing development complexity
Research
ShadowBinding: Realizing Effective Microarchitectures for In-Core Secure Speculation Schemes
Abstract
ShadowBinding proposes effective microarchitectures for state-of-the-art secure speculation schemes, such as Speculative Taint Tracking (STT) and Non-Speculative Data Access (NDA), addressing crucial performance bottlenecks in wide cores. The study reveals that rename-based
Research
Photonic chips developed to improve computing speed and reduce power consumption - Science Media Centre España
Abstract
Researchers have developed innovative photonic chips intended to significantly enhance computing speed and efficiency. These chips utilize light-based processing to overcome the performance bottlenecks and energy constraints of traditional electronic circuits. The
Research
SpikeStream: Accelerating Spiking Neural Network Inference on RISC-V Clusters with Sparse Computation Extensions
Abstract
This paper presents SpikeStream, an optimization technique designed to accelerate Spiking Neural Network (SNN) inference on general-purpose RISC-V multicore clusters using a low-overhead ISA extension for sparse computation streaming. SpikeStream maps weight
Research
CVA6-VMRT: A Modular Approach Towards Time-Predictable Virtual Memory in a 64-bit Application Class RISC-V Processor
Abstract
CVA6-VMRT proposes a modular hardware extension for the open-source RISC-V CVA6 core to achieve time-predictable virtual memory, addressing a critical need in complex autonomous systems. This design incorporates dynamically partitioned Translation Look-aside