Research
Flexing RISC-V Instruction Subset Processors to Extreme Edge
Abstract
This paper introduces an automated methodology for creating RISC-V Instruction Subset Processors (RISSPs) specifically tailored for power and area-constrained Extreme Edge applications, including those using flexible integrated circuits (FlexICs). The approach treats
Research
Hardware vs. Software Implementation of Warp-Level Features in Vortex RISC-V GPU
Abstract
This paper investigates two approaches—hardware acceleration and pure software implementation—for incorporating modern, non-SPMD warp-level features into RISC-V GPUs, specifically using the Vortex architecture. The evaluation demonstrates that implementing these features
Research
Open Challenges for a Production-ready Cloud Environment on top of RISC-V hardware
Abstract
This article, stemming from the Vitamin-V European project, investigates the necessary steps to create a functional, production-ready cloud environment leveraging RISC-V hardware. The authors describe the creation of a prototype RISC-V cluster
Research
Advanced Side-Channel Evaluation Using Contextual Deep Learning-Based Leakage Modeling
Abstract
This work introduces an advanced methodology for side-channel evaluation by leveraging contextual deep learning techniques for leakage modeling. The approach utilizes neural networks to automatically learn and analyze complex, high-dimensional side-channel traces,
News
Exploration platform for RISC-V CHERI designs ... - eeNews Europe
Abstract
A new exploration platform has been developed specifically for prototyping and evaluating RISC-V designs incorporating the CHERI architectural extension. This platform enables researchers to test and verify hardware-enforced memory safety, compartmentalization, and
Research
The Open-Source BlackParrot-BedRock Cache Coherence System
Abstract
This work introduces the open-source BlackParrot-BedRock (BP-BedRock) cache coherence system, built upon the novel BedRock protocol that utilizes canonical MOESIF states while eliminating complex transient states to simplify verification. The research evaluates