Research
e-GPU: An Open-Source and Configurable RISC-V Graphic Processing Unit for TinyAI Applications
Abstract
This work introduces e-GPU, an open-source and highly configurable RISC-V Graphic Processing Unit designed to deliver parallel acceleration to ultra-low-power TinyAI devices. The platform utilizes a lightweight Tiny-OpenCL framework for programming and
A Framework for Designing and Validating Heterogeneous SoC with RISC-V Processor and CGRA
DVHetero: A Framework for Designing and Validating Heterogeneous SoC with RISC-V Processor and CGRA
News
USB module gives bare metal access to RISC-V AI chip ... - eeNews Europe
Abstract
A new USB module has been launched, specifically designed to grant developers bare metal access to a dedicated RISC-V AI processor. This development simplifies low-level programming and debugging, which is essential for
Research
Efficient Implementation of RISC-V Vector Permutation Instructions
Abstract
The efficient hardware implementation of RISC-V Vector (RVV) permutation instructions is complicated by their diverse control mechanisms, despite their necessity for accelerating data-parallel workloads like cryptography. This paper proposes a unified microarchitecture
Research
Assessing Tenstorrent's RISC-V MatMul Acceleration Capabilities
Abstract
This paper evaluates the performance and energy efficiency of the Tenstorrent Grayskull e75 RISC-V accelerator when executing fundamental MatMul operations critical for Large Language Models. Researchers conducted a detailed characterization of the
Research
Assessing Tenstorrent's RISC-V MatMul Acceleration Capabilities
Originally published on ArXiv - Hardware Architecture
Computer Science > Performance
arXiv:2505.06085v3 (cs)
[Submitted on 9 May 2025 (v1), last revised 20 Jun 2025 (this version, v3)]
Title:Assessing Tenstorrent'
Research
Taming Offload Overheads in a Massively Parallel Open-Source RISC-V MPSoC: Analysis and Optimization
Abstract
This study analyzes and optimizes the significant synchronization and communication overheads associated with offloading fine-grained tasks in heterogeneous, massively parallel RISC-V MPSoCs, specifically using the open-source Occamy platform. Through a co-designed approach,