Abstract
The article analyzes the diverse architectural landscape of open-source RISC-V cores, contrasting simple scalar designs with complex superscalar and out-of-order machines. It examines the critical engineering trade-offs between design complexity, power consumption,
Abstract
This work standardizes the proprietary XuanTie C910 Out-of-Order (OoO) RISC-V core for full compliance and introduces CVA6S+, an enhanced dual-issue version of the CVA6 core, achieving a 34.4% performance boost. A
Abstract
This paper presents a novel, unified hardware solution for integrating lightweight and precision-scalable Posit arithmetic into RISC-V Floating Point Units (FPU), while maintaining compatibility with IEEE-754 standards. The implementation uses dedicated posit
Abstract
This paper addresses the critical challenge of compositionality in the RISC-V development flow, which is necessary to fully leverage the modular nature of the ISA specification. The authors introduce "modular SAIL,
Abstract
RISC-V celebrates its 15th anniversary, signifying a major milestone for the open standard Instruction Set Architecture (ISA). The architecture is currently experiencing explosive, rapid global adoption, moving far beyond its academic roots
Abstract
RISC-Q is introduced as an open-source, flexible generator for Quantum Control System-on-Chips (QCSoC) designed to meet the stringent, real-time demands of large-scale qubit systems. It addresses the fragmentation and scalability issues of