Research

Towards Base-Station-On-Chip: Wireless Communication Kernels On A RISC-V Vector Processor (TU Dresden, CeTI) - Semiconductor Engineering

Abstract Researchers from TU Dresden's Center for Tactile Internet (CeTI) are investigating the potential of the RISC-V Vector Processor to efficiently handle demanding wireless communication kernels. This research aims to prove

By Admin 10 Jun 2025 • 2 min read •

Research

FREESS: An Educational Simulator of a RISC-V-Inspired Superscalar Processor Based on Tomasulo's Algorithm (Full Report)

By Admin 9 Jun 2025 • 3 min read •

Research

FREESS: An Educational Simulator of a RISC-V-Inspired Superscalar Processor Based on Tomasulo's Algorithm

Abstract FREESS is a new free, interactive educational simulator designed to teach instruction-level parallelism in advanced computer architecture courses. It models a RISC-V-inspired superscalar processor utilizing an extended Tomasulo's algorithm for

By Admin 9 Jun 2025 • 1 min read •

Research

FREESS: An Educational Simulator of a RISC-V-Inspired Superscalar Processor Based on Tomasulo's Algorithm

Originally published on ArXiv - Hardware Architecture Computer Science > Hardware Architecture arXiv:2506.07665v1 (cs) [Submitted on 9 Jun 2025] Title:FREESS: An Educational Simulator of a RISC-V-Inspired Superscalar Processor Based on

By Admin 9 Jun 2025 • 4 min read •

Research

Chip Industry Technical Paper Roundup: June 9 - Semiconductor Engineering (Full Report)

By Admin 9 Jun 2025 •

News

Momentum Builds on RISC-V European Adoption - EE Times (Full Report)

By Admin 9 Jun 2025 •

Research

Chip Industry Technical Paper Roundup: June 9 - Semiconductor Engineering

Abstract The Chip Industry Technical Paper Roundup for June 9 compiles recent research breakthroughs across various facets of semiconductor technology. The featured papers generally focus on overcoming scaling limitations, implementing advanced 2.5D/

By Admin 9 Jun 2025 • 2 min read •

News

Momentum Builds on RISC-V European Adoption - EE Times

Abstract The article reports a significant acceleration in the adoption of the RISC-V instruction set architecture (ISA) across Europe. This growing momentum is driven by increasing industrial investment and academic collaboration seeking open

By Admin 9 Jun 2025 • 1 min read •

Research

ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors (Full Report)

By Admin 7 Jun 2025 • 3 min read •

Research

ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors

Abstract ASPO (Constraint-Aware Bayesian Optimization) is a novel approach designed to efficiently tune parameters for complex FPGA-based soft processors, overcoming limitations of standard Bayesian Optimization concerning categorical constraints and lengthy optimization times. The

By Admin 7 Jun 2025 • 2 min read •

Research

Design and Implementation of a RISC-V SoC with Custom DSP Accelerators for Edge Computing (Full Report)

By Admin 7 Jun 2025 • 3 min read •

Research

Design and Implementation of a RISC-V SoC with Custom DSP Accelerators for Edge Computing

Abstract This paper analyzes the performance of a custom RISC-V SoC implementation, utilizing the RV32I base ISA with M and A extensions, specifically targeting edge computing applications. Through cycle-accurate simulation, the pipelined design

By Admin 7 Jun 2025 • 1 min read •