News

Indian RISC-V Startup Slashes Design Time to Minutes - EE Times

Abstract An Indian RISC-V startup has achieved a significant technological breakthrough by developing a system that drastically reduces processor design time. This innovation allows users to configure and generate customized RISC-V core IP

By Admin 17 Jun 2025 • 2 min read •

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News

The Rise of RISC-V ... - eeNews Europe (Full Report)

By Admin 16 Jun 2025 •

News

The Rise of RISC-V ... - eeNews Europe

Abstract The article details the substantial acceleration and maturation of the RISC-V open Instruction Set Architecture (ISA), positioning it as a significant challenger to proprietary alternatives like Arm. This rise is fueled by

By Admin 16 Jun 2025 • 2 min read •

Research

FeNN: A RISC-V vector processor for Spiking Neural Network acceleration (Full Report)

By Admin 13 Jun 2025 • 3 min read •

Research

FeNN: A RISC-V vector processor for Spiking Neural Network acceleration

Abstract The FeNN processor is a novel RISC-V-based soft vector processor specifically tailored for simulating energy-efficient Spiking Neural Networks (SNNs) on FPGAs. Unlike mainstream accelerators, FeNN is optimized for the low arithmetic intensity

By Admin 13 Jun 2025 • 2 min read •

Research

FractalSync: Lightweight Scalable Global Synchronization of Massive Bulk Synchronous Parallel AI Accelerators (Full Report)

By Admin 13 Jun 2025 • 3 min read •

Research

FractalSync: Lightweight Scalable Global Synchronization of Massive Bulk Synchronous Parallel AI Accelerators

Abstract FractalSync is a novel hardware-accelerated synchronization mechanism designed to address the challenges of coordinating massive parallel processing elements in Bulk Synchronous Parallel (BSP) AI accelerators. Integrated into the RISC-V based MAGIA platform,

By Admin 13 Jun 2025 • 2 min read •

Research

Towards Zero-Stall Matrix Multiplication on Energy-Efficient RISC-V Clusters for Machine Learning Acceleration (Full Report)

By Admin 12 Jun 2025 • 3 min read •

Research

Towards Zero-Stall Matrix Multiplication on Energy-Efficient RISC-V Clusters for Machine Learning Acceleration

Abstract This paper presents microarchitectural optimizations for energy-efficient RISC-V clusters aimed at achieving near zero-stall matrix multiplication for machine learning workloads. Key innovations include "zero-overhead loop nests" and a novel "

By Admin 12 Jun 2025 • 2 min read •

News

RISC-V’s Increasing Influence - Semiconductor Engineering (Full Report)

By Admin 12 Jun 2025 •

News

RISC-V’s Increasing Influence - Semiconductor Engineering

Abstract RISC-V is rapidly increasing its influence across the semiconductor industry, expanding adoption beyond academic and niche markets into high-volume segments like data centers, automotive, and consumer electronics. This growth is fundamentally driven

By Admin 12 Jun 2025 • 2 min read •

Research

Towards Base-Station-On-Chip: Wireless Communication Kernels On A RISC-V Vector Processor (TU Dresden, CeTI) - Semiconductor Engineering (Full Report)

By Admin 10 Jun 2025 •