🔒 Members
Research
HW/SW Co-Design to Retarget the Compiler For RISC-V Custom Instructions (Tampere Univ.) - Semiconductor Engineering
Abstract
The research by Tampere University introduces an HW/SW co-design methodology aimed at efficiently integrating custom instruction set extensions (ISEs) into RISC-V cores. This approach specifically focuses on solving the typically time-consuming
News
RISC-V: Shaping the Future of Mobility with Open Standards - EE Times
Abstract
RISC-V is emerging as the essential open standard architecture driving the future of mobility, specifically targeting advanced automotive applications like ADAS and high-performance computing in vehicles. The modular and customizable nature of
News
Condor Technology To Fly “Cuzco” RISC-V CPU Into The Datacenter - The Next Platform
Abstract
Condor Technology is making a significant push into the competitive datacenter market with the introduction of its high-performance RISC-V CPU, codenamed "Cuzco." This development signals the maturity of the RISC-V
Research
SuperUROP: An FPGA-Based Spatial Accelerator for Sparse Matrix Operations
Abstract
Solving sparse linear systems is critical in numerical methods but suffers from poor data reuse and complex dependencies on current hardware. This paper presents SuperUROP, an FPGA implementation of the Azul spatial
Research
TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification
Abstract
TurboFuzz is an end-to-end hardware-accelerated verification framework that leverages a single FPGA to integrate the entire Test Generation, Simulation, and Coverage Feedback loop for modern processors. This architecture eliminates high host-FPGA communication
Research
Decentor-V: Lightweight ML Training on Low-Power RISC-V Edge Devices
Abstract
This paper introduces Decentor-V, a framework that enables lightweight Machine Learning training directly on low-power RISC-V edge devices, overcoming the architectural limitation imposed by the absence of dedicated Floating-Point Units (FPUs). By