News

Google, AWS, and NASA to Keynote RISC-V Summit North America 2025 - Embedded Computing Design

Abstract The RISC-V Summit North America 2025 will prominently feature keynotes from major technology and government powerhouses, specifically Google, Amazon Web Services (AWS), and NASA. This high-profile participation validates RISC-V's transformation

By Admin 24 Sep 2025 • 2 min read •

News

RISC-V Acceleration for Deep Learning at the Edge - Electropages (Full Report)

By Admin 23 Sep 2025 •

Research

Chip Industry Technical Paper Roundup: Sept 23 - Semiconductor Engineering (Full Report)

By Admin 23 Sep 2025 •

News

RISC-V Acceleration for Deep Learning at the Edge - Electropages

Abstract The article discusses the growing utilization of the open RISC-V Instruction Set Architecture (ISA) coupled with specialized hardware accelerators to meet the demanding requirements of Deep Learning inference at the edge. By

By Admin 23 Sep 2025 • 2 min read •

Research

Chip Industry Technical Paper Roundup: Sept 23 - Semiconductor Engineering

Abstract The analysis of the 'Chip Industry Technical Paper Roundup: Sept 23' is incomplete because the actual text content of the summarized technical papers was not provided, only the title and

By Admin 23 Sep 2025 • 1 min read •

Research

Chiplet-Based RISC-V SoC with Modular AI Acceleration (Full Report)

By Admin 22 Sep 2025 • 3 min read •

Research

Chiplet-Based RISC-V SoC with Modular AI Acceleration

Abstract This paper introduces a novel chiplet-based RISC-V System-on-Chip designed to overcome the low manufacturing yields and rigidity of monolithic edge AI devices by utilizing a 30mm x 30mm silicon interposer. The architecture

By Admin 22 Sep 2025 • 2 min read •

Research

Automatic Microarchitecture-Aware Custom Instruction Design for RISC-V Processors (Full Report)

By Admin 19 Sep 2025 • 3 min read •

Research

Automatic Microarchitecture-Aware Custom Instruction Design for RISC-V Processors

Abstract Designing Application-Specific Instruction Set Processors (ASIPs) requires the manual identification of performance-enhancing custom instructions, a process addressed by this work's new automation tool. The paper introduces CIDRE (Custom Instruction Designer

By Admin 19 Sep 2025 • 2 min read •

Research

MaRVIn: A Cross-Layer Mixed-Precision RISC-V Framework for DNN Inference, from ISA Extension to Hardware Acceleration (Full Report)

By Admin 18 Sep 2025 • 3 min read •

Research

MaRVIn: A Cross-Layer Mixed-Precision RISC-V Framework for DNN Inference, from ISA Extension to Hardware Acceleration

Abstract MaRVIn is a cross-layer hardware-software co-design framework that introduces novel ISA extensions and micro-architectural enhancements to optimize mixed-precision Deep Neural Network (DNN) inference on RISC-V processors. It tackles the inefficiency of standard

By Admin 18 Sep 2025 • 2 min read •

News

RISC-V: Shaping the Future of Mobility with Open Standards - EE Times (Full Report)

By Admin 16 Sep 2025 •