Research
A High-Efficiency SoC for Next-Generation Mobile DNA Sequencing
Abstract
This paper presents a high-efficiency System-on-Chip (SoC) designed to enable truly mobile, real-time DNA sequencing by overcoming the computational limits of current hand-sized machines that rely on external processing. The SoC is
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RISC-V set to announce 25% market penetration — open-standard ISA is ahead of schedule, securing fast-growing silicon footprint - Tom's Hardware
Abstract
The open-standard RISC-V Instruction Set Architecture (ISA) is reportedly set to announce a significant achievement: 25% market penetration globally. This milestone demonstrates that RISC-V's growth is accelerating faster than predicted,
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What Meta’s Purchase of Rivos Says About RISC-V - HPCwire
Abstract
Meta's strategic acquisition of Rivos, a startup specializing in high-performance RISC-V chip design, validates the open-source architecture's maturity for demanding data center and AI workloads. This move allows
Research
A Dense and Efficient Instruction Set Architecture Encoding
Abstract
This paper introduces Scry, a novel and experimental Instruction Set Architecture (ISA) designed to maximize instruction density and encoding efficiency for modern processor implementations. Scry achieves instruction-feature parity with RISC-V's
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Terasic Announces Starter Kit Featuring RISC-V Nios V Processor and Software Bundle - LinuxGizmos.com
Abstract
Terasic has announced the release of a new starter kit centered around the RISC-V Nios V processor, significantly aiding developers in exploring this architecture. The kit is packaged with essential hardware components