Research
ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors
Abstract
ShuffleV is a novel microarchitectural defense strategy developed to counter Electromagnetic Side-Channel Attacks (EM SCAs) by adopting a Moving Target Defense (MTD) philosophy. It integrates hardware units into the open-source RISC-V core
Research
Near-Optimal Cache Sharing through Co-Located Parallel Scheduling of Threads
Abstract
This work introduces a novel mechanism, Co-Located Parallel Scheduling, aimed at achieving near-optimal efficiency in shared cache utilization among competing threads. The innovation focuses on intelligently grouping and scheduling threads whose memory
Research
A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems
Abstract
This paper introduces a novel Direct Memory Access Controller (DMAC) specifically optimized to efficiently handle arbitrary transfers of small unit sizes, addressing the inefficiency of classical descriptor-based DMACs in heterogeneous computing environments.
News
Forlinx OK153-S SBC Combines Cortex-A7 and RISC-V Cores for Real-Time I/O Interfaces - LinuxGizmos.com
Abstract
The Forlinx OK153-S Single Board Computer (SBC) introduces a notable heterogeneous architecture combining an ARM Cortex-A7 core with a specialized RISC-V core. This design leverages the strengths of both platforms, using the
News
Why RISC-V + Blockchain Is the Conversation I’ve Been Waiting to Have - EE Times
Abstract
The EE Times article highlights the critical intersection of the open-source RISC-V architecture and blockchain technology. This convergence is positioned to dramatically enhance hardware security and supply chain transparency, solving pervasive trust
Research
Sequencing on Silicon: AI SoC Design for Mobile Genomics at the Edge
Abstract
This paper presents a specialized CMOS System-on-Chip (SoC) designed to handle the extremely high data rates of mobile nanopore DNA sequencing, advancing genomic analysis at the edge. The proposed architecture employs a