Research
Hardware-Aware Neural Network Compilation with Learned Optimization: A RISC-V Accelerator Approach
Abstract
The XgenSilicon ML Compiler is an automated end-to-end framework that optimizes high-level machine learning models into highly efficient RISC-V assembly code for custom ASIC accelerators. This system unifies software and hardware cost
Research
Bespoke Co-processor for Energy-Efficient Health Monitoring on RISC-V-based Flexible Wearables
Abstract
This work introduces a highly energy-efficient, mechanically flexible RISC-V system designed for on-body health monitoring, addressing the challenges posed by the power constraints and limited gate counts of flexible electronics. The core
Research
MultiVic: A Time-Predictable RISC-V Multi-Core Processor Optimized for Neural Network Inference
Abstract
MultiVic is a novel, time-predictable RISC-V multi-core vector processor designed to meet the high-performance and strict predictability requirements of neural network inference in real-time systems. The architecture ensures predictable timing behavior by
Research
TT-Edge: A Hardware-Software Co-Design for Energy-Efficient Tensor-Train Decomposition on Edge AI
Abstract
TT-Edge is a hardware-software co-designed framework engineered to overcome the high latency and energy costs associated with Tensor Train Decomposition (TTD) on resource-constrained edge AI devices. It achieves this by offloading compute-intensive
Research
FiCABU: A Fisher-Based, Context-Adaptive Machine Unlearning Processor for Edge AI
Abstract
FiCABU (Fisher-based Context-Adaptive Balanced Unlearning) is a novel software-hardware co-design that integrates efficient machine unlearning capabilities into a RISC-V edge AI processor. This system employs Context-Adaptive Unlearning, starting edits from back-end layers,
News
Arteris and Alibaba (BABA) XuanTie Expand RISC-V Collaboration - Yahoo Finance
Abstract
Arteris and Alibaba (BABA) XuanTie have announced an expanded collaboration focused on accelerating the development within the RISC-V ecosystem. This partnership aims to deeply integrate Arteris' high-performance Network-on-Chip (NoC) technology with