Research
Toward Open-Source Chiplets for HPC and AI: Occamy and Beyond
Abstract
This paper presents a roadmap for open-source RISC-V chiplet systems designed for high-performance computing (HPC) and artificial intelligence (AI), aiming to match the performance of proprietary architectures. The initiative introduces Occamy, the
Research
A Configurable Mixed-Precision Fused Dot Product Unit for GPGPU Tensor Computation
Abstract
This paper introduces a scalable mixed-precision fused dot product unit designed to overcome the suboptimal throughput of discrete arithmetic units in GPGPUs for Deep Learning workloads. Integrated into the open-source RISC-V Vortex
News
RISC-V And Its Modularity Shine Across Applications - embedded.com
Abstract
The article emphasizes that RISC-V’s success is intrinsically linked to its open standard and profound architectural modularity, enabling widespread adoption across diverse application spaces. This inherent flexibility permits designers to tailor
Research
CoroAMU: Unleashing Memory-Driven Coroutines through Latency-Aware Decoupled Operations
Abstract
CoroAMU is a hardware-software co-designed system addressing severe memory latency issues in data-intensive applications running on disaggregated memory systems. The system features a compiler that optimizes coroutine management by minimizing context and
RISC-V
7 Things I Learned at RISC-V Summit North America 2025
Originally published on RISC-V International News
* Tom GallVice President of Technology, RISC-V InternationalIndustry veteran Tom shapes the overall technical strategy for the RISC-V Instruction Set Architecture (ISA). An alum of IBM and Linaro,
News
Sailing Through the RISC-V Movement Across Continents - embedded.com
Abstract
The article tracks the accelerated global momentum of the open-source RISC-V Instruction Set Architecture (ISA), highlighting its widespread adoption across various continents and industries. It emphasizes how this movement is transitioning from