Research
The Configuration Wall: Characterization and Elimination of Accelerator Configuration Overhead
Abstract
This paper characterizes the 'Configuration Wall,' a critical bottleneck where the latency of setting up hardware accelerators consumes a dominant portion of the total execution time for fine-grained tasks. The
Research
Sequential Specifications for Precise Hardware Exceptions
Abstract
The paper introduces a formal methodology, termed "Sequential Specifications," designed to rigorously define and guarantee precise hardware exceptions, even in aggressive out-of-order processor implementations. This approach disentangles the complex specification
Research
CHERI-SIMT: Implementing Capability Memory Protection in GPUs
Abstract
CHERI-SIMT introduces the first unified architecture to integrate the CHERI Capability Hardware Enhanced RISC Instructions model directly into the Single Instruction, Multiple Threads (SIMT) execution pipeline of GPUs. This innovation addresses the
Research
A Data-Driven Dynamic Execution Orchestration Architecture
Abstract
This paper presents a novel Data-Driven Dynamic Execution Orchestration Architecture designed to enhance processor efficiency and performance predictability. The core innovation involves using runtime data insights to dynamically manage and schedule execution
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News
Qualcomm acquires Ventana Micro Systems to strengthen RISC-V CPU capabilities - digitimes
Abstract
Qualcomm has executed a significant strategic acquisition, purchasing Ventana Micro Systems to substantially strengthen its internal capabilities related to RISC-V CPU development. This move signals Qualcomm's aggressive intent to deepen
RISC-V
Ocelot3: Full Vector “V” Extension for BOOM
Abstract
Ocelot3 is the latest iteration of the open-source project integrating vector support into the BOOM RISC-V core, achieving full compatibility with the RVV 1.0 specification. This generation features a decoupled Vector
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