Abstract This paper presents an open-source soft processor designed for tight integration within an FPGA overlay framework to facilitate full application acceleration. Leveraging the RISC-V instruction set and a 4-stage pipeline, the design

Abstract GRVI Phalanx is a massively parallel framework combining the FPGA-efficient RISC-V RV32I soft processor (GRVI) with a high-density parallel processor and accelerator array (Phalanx). This architecture utilizes shared memory clusters interconnected by

Abstract This paper introduces System Hyper Pipelining (SHP), an advanced extension of C-Slow Retiming, applied to the Programming Elements (PEs) of a Coarse-Grained Reconfigurable Architecture (CGRA). SHP enables dynamic management of execution threads—