Research
NTX: An Energy-efficient Streaming Accelerator for Floating-point Generalized Reduction Workloads in 22nm FD-SOI
Abstract
NTX is an energy-efficient streaming accelerator designed for 32-bit floating-point generalized reduction workloads, including training large Deep Neural Networks. Implemented in 22nm FD-SOI technology and orchestrated by a RISC-V core, the accelerator
Research
JuxtaPiton: Enabling Heterogeneous-ISA Research with RISC-V and SPARC FPGA Soft-cores
Abstract
JuxtaPiton is introduced as the first open-source, general-purpose, heterogeneous-ISA processor designed to enable crucial energy efficiency research. It integrates a small RISC-V core alongside a modified OpenSPARC T1 core within the OpenPiton
Research
Formally Verifying WARP-V, an Open-Source TL-Verilog RISC-V Core Generator
Abstract
This paper details the formal verification of WARP-V, an open-source RISC-V core generator developed using the timing-abstract, transaction-level TL-Verilog methodology. The verification employed the established riscv-formal framework, investigating the synergy between transaction-level
Research
RISC-V: More Than a Core - Semiconductor Engineering
Abstract
The article analyzes the maturation of the RISC-V ecosystem, arguing that its impact now extends far beyond the foundational Instruction Set Architecture (ISA). It emphasizes the critical role of surrounding elements, including
Research
CIDPro: Custom Instructions for Dynamic Program Diversification
Abstract
CIDPro is a novel framework that uses dynamic program diversification and custom instruction generation to mitigate timing side-channel attacks in embedded systems. It integrates the LLVM compiler and the RISC-V FPGA soft-processor,
Research
The BaseJump Manycore Accelerator Network
Abstract
The BaseJump Manycore Accelerator Network is an open-source, mesh-based On-Chip-Network (OCN) developed using over 20 years of manycore architecture expertise. This scalable network served as the communication backbone for the 16nm 511-core