Research
Boosting the Bounds of Symbolic QED for Effective Pre-Silicon Verification of Processor Cores
Abstract
This work introduces a novel pre-silicon verification approach that systematically leverages Symbolic Quick Error Detection (SQED) combined with symbolic starting states to drastically improve the detection of deep logic bugs and Hardware
Research
PERI: A Posit Enabled RISC-V Core
Abstract
This paper introduces PERI, the first Posit Enabled RISC-V core, which integrates the advanced Posit arithmetic format—a superior alternative to IEEE 754—into the extensible RISC-V ISA. The implementation leverages the
Research
Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22 nm FD-SOI
Abstract
Ara is a highly scalable and energy-efficient 64-bit vector processor based on the RISC-V vector extension (v0.5 draft), realized in 22 nm FD-SOI technology. Its lane-based microarchitecture achieves clock speeds exceeding
Research
Fast TLB Simulation for RISC-V Systems
Abstract
This paper introduces a novel, fast TLB simulation framework specifically designed for exploring Translation Lookaside Buffer (TLB) behaviors in multi-core RISC-V systems. Integrated into the QEMU dynamic binary translated emulator, the framework
Research
The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-ready 1.7GHz 64bit RISC-V Core in 22nm FDSOI Technology
Abstract
This paper presents a thorough energy and performance analysis of Ariane, an open-source, single-issue 64-bit RISC-V core implemented for application-class processing and supporting the Linux OS. Taped-out in 22nm FDSOI technology, the
Research
Formal Verification Of RISC-V Cores - Semiconductor Engineering
Abstract
The article emphasizes the critical role of Formal Verification (FV) in the development lifecycle of RISC-V cores, ensuring functional correctness and adherence to the Instruction Set Architecture (ISA). It details how FV