Research

SSR: A Stall Scheme Reducing Bubbles in Load-Use Hazard of RISC-V Pipeline

Abstract This paper introduces SSR (Stall Scheme Reducing bubbles), a microarchitectural modification designed to reduce performance degradation caused by load-use hazards in RISC-V pipelines. The proposed method replaces the traditional ID-EXE stage stall

By Admin 23 Dec 2019 • 2 min read •

Research

Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores (Full Report)

By Admin 19 Nov 2019 • 3 min read •

Research

Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores

Abstract Stream Semantic Registers (SSR) is a lightweight, non-invasive RISC-V Instruction Set Architecture extension designed to overcome the von Neumann bottleneck in energy-efficient single-issue cores. SSR achieves full compute utilization by implicitly encoding

By Admin 19 Nov 2019 • 2 min read •

Research

Using Name Confusion to Enhance Security (Full Report)

By Admin 5 Nov 2019 • 3 min read •

Research

Using Name Confusion to Enhance Security

Abstract The paper introduces Name Confusion, a novel security concept implemented by the Phantom Name System (PNS), designed to thwart multiple classes of code-reuse attacks. PNS provides multiple randomized virtual addresses (N mappings)

By Admin 5 Nov 2019 • 2 min read •

Research

Sapphire: A Configurable Crypto-Processor for Post-Quantum Lattice-based Protocols (Full Report)

By Admin 16 Oct 2019 • 4 min read •

Research

Sapphire: A Configurable Crypto-Processor for Post-Quantum Lattice-based Protocols

Abstract Sapphire is a configurable crypto-processor designed to accelerate computationally intensive lattice-based post-quantum cryptography (PQC) protocols on low-power embedded devices. Utilizing optimizations such as a SHA-3-based PRNG and a single-port RAM NTT memory

By Admin 16 Oct 2019 • 2 min read •

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Research

Researchers build first 16-bit, 14,000-transistor carbon nanotube chip - bit-tech.net (Full Report)

By Admin 29 Aug 2019 •

Research

Researchers build first 16-bit, 14,000-transistor carbon nanotube chip - bit-tech.net

Abstract Researchers have successfully engineered the world's first 16-bit microprocessor built entirely using carbon nanotube (CNT) technology. This groundbreaking chip integrates 14,000 transistors, marking a significant milestone in demonstrating the

By Admin 29 Aug 2019 • 1 min read •

Research

Researchers build first 16-bit, 14,000-transistor carbon nanotube chip - Bit-Tech

Originally published on Google News - RISC-V Research Researchers build first 16-bit, 14,000-transistor carbon nanotube chip  Bit-Tech

By Admin 29 Aug 2019 •

Research

BRISC-V: An Open-Source Architecture Design Space Exploration Toolbox (Full Report)

By Admin 27 Aug 2019 • 3 min read •

Research

BRISC-V: An Open-Source Architecture Design Space Exploration Toolbox

Abstract BRISC-V is an open-source, parameterized, and synthesizable register-transfer level (RTL) platform designed for comprehensive architecture design space exploration of RISC-V systems. It provides highly modular components spanning simple single-core designs to complex

By Admin 27 Aug 2019 • 2 min read •