Research

The gem5 Simulator: Version 20.0+

Abstract This paper introduces the gem5 Simulator: Version 20.0+, detailing the evolution of this popular open-source computer architecture research tool over the last nine years. The simulator provides high-fidelity, cycle-level modeling capable

By Admin 7 Jul 2020 • 2 min read •

Research

FPnew: An Open-Source Multi-Format Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing (Full Report)

By Admin 3 Jul 2020 • 3 min read •

Research

FPnew: An Open-Source Multi-Format Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing

Abstract FPnew is a highly configurable, open-source transprecision floating-point unit (TP-FPU) architecture designed to enable energy-proportional computing by handling a wide range of standard and custom FP formats. The unit extends the RISC-V

By Admin 3 Jul 2020 • 2 min read •

Research

Arnold: an eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End-Nodes (Full Report)

By Admin 25 Jun 2020 • 3 min read •

Research

Arnold: an eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End-Nodes

Abstract Arnold is an energy-efficient, flexible RISC-V System-on-Chip (SoC) designed for demanding IoT end-nodes, coupling a high-performance MCU with an embedded FPGA (eFPGA) in 22nm GF22FDX technology. The SoC achieves exceptional power efficiency

By Admin 25 Jun 2020 • 2 min read •

Research

CLARINET: A RISC-V Based Framework for Posit Arithmetic Empiricism (Full Report)

By Admin 30 May 2020 • 3 min read •

Research

CLARINET: A RISC-V Based Framework for Posit Arithmetic Empiricism

Abstract CLARINET is an open-source, RISC-V based processor framework designed for the empirical validation of posit arithmetic as a potential replacement for the IEEE 754 floating-point standard. The framework incorporates 'Melodica,'

By Admin 30 May 2020 • 2 min read •

Research

Accelerate Cycle-Level Full-System Simulation of Multi-Core RISC-V Systems with Binary Translation (Full Report)

By Admin 22 May 2020 • 3 min read •

Research

Accelerate Cycle-Level Full-System Simulation of Multi-Core RISC-V Systems with Binary Translation

Abstract This paper presents a novel multi-purpose simulator that accelerates cycle-level full-system simulation of multi-core RISC-V systems using binary translation. The tool successfully addresses the perennial trade-off between simulation accuracy and performance, achieving

By Admin 22 May 2020 • 1 min read •

Research

A Lightweight Isolation Mechanism for Secure Branch Predictors (Full Report)

By Admin 17 May 2020 • 3 min read •

Research

A Lightweight Isolation Mechanism for Secure Branch Predictors

Abstract This paper presents a lightweight, randomization-based mechanism to isolate content within shared branch predictors, counteracting cross-process malicious training and perception attacks. The solution avoids performance-heavy methods like flushing or physical isolation by

By Admin 17 May 2020 • 2 min read •

Research

LiteX: an open-source SoC builder and library based on Migen Python DSL (Full Report)

By Admin 5 May 2020 • 3 min read •