Research

Enabling Virtual Memory Research on RISC-V with a Configurable TLB Hierarchy for the Rocket Chip Generator

Abstract This work enhances the RISC-V Rocket Chip Generator by implementing a configurable, set-associative Translation Lookaside Buffer (TLB) hierarchy within its Memory Management Unit. This innovation lifts the previous restrictions of fixed L1/

By Admin 16 Sep 2020 • 2 min read •

Research

A transprecision floating-point cluster for efficient near-sensor data analytics (Full Report)

By Admin 27 Aug 2020 • 3 min read •

Research

A transprecision floating-point cluster for efficient near-sensor data analytics

Abstract This paper presents a multi-core computing cluster based on the open-source RISC-V architecture, utilizing transprecision floating-point arithmetic for efficient near-sensor data analytics. The system achieves a minimum power budget through parallelization, sub-word

By Admin 27 Aug 2020 • 2 min read •

Research

Manticore: A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing (Full Report)

By Admin 14 Aug 2020 • 3 min read •

Research

Manticore: A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing

Abstract Manticore is a 4096-core RISC-V chiplet architecture designed for ultra-efficient, general-purpose data-parallel floating-point (FP) workloads. It utilizes Snitch clusters, where small integer cores control large FPUs, achieving FPU utilization above 90% through

By Admin 14 Aug 2020 • 2 min read •

Research

BasicBlocker: ISA Redesign to Make Spectre-Immune CPUs Faster (Full Report)

By Admin 31 Jul 2020 • 3 min read •

Research

BasicBlocker: ISA Redesign to Make Spectre-Immune CPUs Faster

Abstract This paper introduces BasicBlocker, a novel ISA redesign that enables non-speculative CPUs to achieve performance comparable to systems utilizing speculative execution, thereby addressing Spectre-class attacks robustly. BasicBlocker is a generic modification applicable

By Admin 31 Jul 2020 • 2 min read •

Research

Klessydra-T: Designing Vector Coprocessors for Multi-Threaded Edge-Computing Cores (Full Report)

By Admin 17 Jul 2020 • 3 min read •

Research

Klessydra-T: Designing Vector Coprocessors for Multi-Threaded Edge-Computing Cores

Abstract Klessydra-T investigates methodologies for designing vector coprocessors tailored for Interleaved-Multi-Threading (IMT) RISC-V cores targeting edge-computing applications. The core goal is to efficiently accelerate computation-intensive kernels, such as AI convolutions and matrix multiplication,

By Admin 17 Jul 2020 • 2 min read •

Research

Enabling Mixed-Precision Quantized Neural Networks in Extreme-Edge Devices (Full Report)

By Admin 15 Jul 2020 • 3 min read •

Research

Enabling Mixed-Precision Quantized Neural Networks in Extreme-Edge Devices

Abstract This work introduces a critical extension to the PULP-NN library optimized for accelerating mixed-precision Quantized Neural Networks (QNNs) on ultra-low-power RISC-V edge devices. Featuring 27 highly optimized kernels supporting 8-bit, 4-bit, and

By Admin 15 Jul 2020 • 2 min read •

Research

The gem5 Simulator: Version 20.0+ (Full Report)

By Admin 7 Jul 2020 • 4 min read •