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Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning
Abstract
This work addresses microarchitectural timing channels by proposing a systematic hardware defense mechanism based on full temporal partitioning. Leveraging the RISC-V ISA, the authors introduce a new temporal fence instruction, fence.t,
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RISC-V AI Chips Will Be Everywhere - IEEE Spectrum
Abstract
RISC-V architecture is rapidly emerging as the foundation for next-generation AI accelerators, promising ubiquity across diverse computing domains. This proliferation is driven by RISC-V's intrinsic flexibility, allowing developers to implement
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CVA6's Data cache: Structure and Behavior
Abstract
This paper addresses the critical lack of detailed documentation regarding the data cache microarchitecture within the widely used RISC-V CVA6 core, a necessary precursor for successful security research. Since microarchitectural attacks like
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CVA6's Data cache: Structure and Behavior
Originally published on ArXiv - Hardware Architecture
Computer Science > Cryptography and Security
arXiv:2202.03749v3 (cs)
[Submitted on 8 Feb 2022 (v1), last revised 5 Jul 2022 (this version, v3)]
Title:CVA6&
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Do You Know For Sure Your RISC-V RTL Doesn’t Contain Any Surprises? - Semiconductor Engineering
Abstract
The article critically examines the challenges associated with rigorous verification and validation of RISC-V Register Transfer Level (RTL) designs. It highlights the potential for hidden bugs, security vulnerabilities, or unintended features—termed
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DuVisor: a User-level Hypervisor Through Delegated Virtualization
Abstract
DuVisor introduces the concept of "delegated virtualization" to fundamentally redesign hypervisor architecture, achieving a purely user-level hypervisor by separating the control plane from the data plane. This design allows DuVisor