Research

ProcessorFuzz: Guiding Processor Fuzzing using Control and Status Registers

Abstract ProcessorFuzz is a novel hardware fuzzer designed for efficient verification of complex processor Register-Transfer Level (RTL) designs. It introduces a CSR-transition coverage metric that guides the fuzzing process by monitoring Control and

By Admin 5 Sep 2022 • 2 min read •

Research

Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters (Full Report)

By Admin 2 Sep 2022 • 3 min read •

Research

Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters

Abstract This paper introduces the concept of "Soft Tiles" to capture and exploit physical implementation flexibility within tightly-coupled processing clusters used in modern high-performance architectures. The research explores how varying the

By Admin 2 Sep 2022 • 2 min read •

Research

Technical Paper Round-Up: Aug 23 - Semiconductor Engineering

Originally published on Google News - RISC-V Research Technical Paper Round-Up: Aug 23  Semiconductor Engineering

By Admin 23 Aug 2022 •

Research

Kraken: A Direct Event/Frame-Based Multi-sensor Fusion SoC for Ultra-Efficient Visual Processing in Nano-UAVs (Full Report)

By Admin 18 Aug 2022 • 3 min read •

Research

Kraken: A Direct Event/Frame-Based Multi-sensor Fusion SoC for Ultra-Efficient Visual Processing in Nano-UAVs

Abstract Kraken is an ultra-low-power, heterogeneous System-on-Chip (SoC) fabricated in 22nm FDX technology designed to enable complex, autonomous visual tasks for Nano-UAVs under tight power constraints. The chip achieves high-speed, multi-functional visual processing

By Admin 18 Aug 2022 • 2 min read •

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Research

Implementing Cryptographic Algorithms for the RISC-V Instruction Set Architecture in Two Cases - Semiconductor Engineering (Full Report)

By Admin 18 Aug 2022 •

Research

Implementing Cryptographic Algorithms for the RISC-V Instruction Set Architecture in Two Cases - Semiconductor Engineering

Abstract The analyzed work details the successful implementation and evaluation of core cryptographic algorithms tailored for the RISC-V Instruction Set Architecture. The research specifically contrasts performance and complexity across 'Two Cases,'

By Admin 18 Aug 2022 • 2 min read •

Research

SiFive Is Leading The Way For Innovation On RISC-V - Forbes (Full Report)

By Admin 8 Aug 2022 •

Research

SiFive Is Leading The Way For Innovation On RISC-V - Forbes

Abstract The article highlights SiFive's pivotal role in spearheading innovation within the RISC-V ecosystem, transforming the open instruction set architecture into a commercially viable, high-performance solution. SiFive is driving RISC-V adoption

By Admin 8 Aug 2022 • 2 min read •

Research

An Enclave-based TEE for SE-in-SoC in RISC-V Industry (Full Report)

By Admin 7 Aug 2022 • 3 min read •

Research

An Enclave-based TEE for SE-in-SoC in RISC-V Industry

Abstract This work introduces an Enclave-based Trusted Execution Environment (TEE) designed to secure integrated Secure Elements (SE) within RISC-V Systems-on-Chip (SoC). Addressing the rising complexity and security flaws of traditional SE-in-SoC designs, the

By Admin 7 Aug 2022 • 2 min read •