Research
AXI-Pack: Near-Memory Bus Packing for Bandwidth-Efficient Irregular Workloads
Abstract
AXI-Pack is proposed as an extension to the ARM AXI4 protocol designed to address the bandwidth inefficiencies of irregular memory streams (strided and indirect accesses) in on-chip interconnects. This extension introduces specialized
Research
Trusted Hart for Mobile RISC-V Security
Abstract
This paper addresses the critical need for a robust Trusted Execution Environment (TEE) within future RISC-V mobile devices, contrasting with the established Arm security architecture. The authors propose a novel security architecture
Research
RISC-V Is Far from Being an Alternative to x86 and Arm in HPC - HPCwire
Abstract
This article critically assesses the current state of RISC-V adoption in High-Performance Computing (HPC), concluding that the open-source ISA remains significantly behind established architectures like x86 and Arm. The primary barriers to
Research
The BlackParrot BedRock Cache Coherence System
Abstract
This paper presents BP-BedRock, an open-source, directory-based MOESIF cache coherence system implemented within the BlackParrot 64-bit RISC-V multicore processor. The system notably includes both a fixed-function FSM and a microcode programmable coherence
Research
Microprocessor Design with Dynamic Clock Source and Multi-Width Instructions
Abstract
This paper introduces the design of a novel 32-bit microprocessor based on the RISC-V Instruction Set Architecture. The key innovation is the utilization of a dynamic clock source, which significantly enhances efficiency
