IEEE
Research
TeraPool: A Physical Design Aware, 1024 RISC-V Cores Shared-L1-Memory Scaled-Up Cluster Design With High Bandwidth Main Memory Link
Abstract
The TeraPool project introduces a highly scaled-up cluster architecture integrating 1024 RISC-V cores optimized for parallelism. Its key innovation is a physically design-aware implementation featuring a shared-L1-memory
Research
XiangShan: An Open Source Project for High-Performance RISC-V Processors Meeting Industrial-Grade Standards
Abstract
The XiangShan project introduces a major open-source initiative dedicated to building high-performance RISC-V processors. Crucially, the design targets industrial-grade standards, ensuring the necessary reliability and robustness for commercial