Stop Paying by the Letter: Accelerating Full-Chip RTL Simulation with Host-Side Tokenized Logging

AI Analysis

Abstract

Key Highlights

• Eliminates on-core radix conversion and significantly reduces MMIO bus transactions and stalls.
• Achieves 100% bit-exact output parity with zero simulator memory overhead.
• Saves 1,314.85 simulator CPU hours and 1,670.75 wall-clock hours per regression pass across 858 full-chip test pairs.
• Reduces median single-test CPU time by 41.51% (Subsystem Suite A) and 21.33% (Subsystem Suite B).
• Boosts mean effective simulator throughput by +24.02% (Subsystem Suite A) and +19.60% (Subsystem Suite B) per CPU second.
• Shrinks instruction traces by 42.84% and waveform dumps by 28.82% (medians).
• Exposes latent multi-core firmware synchronization races previously masked by logging delays.

Technical Details

• The architecture uses link-time ELF format-string virtual addresses as token IDs.
• A fixed 32-bit word-aligned slot protocol is used for transmitting tokens and arguments, identical across Arm, RISC-V, and DSP cores.
• On-core logging collapses to a single-pass specifier scan and (1+S) MMIO word writes, removing radix conversion.
• A SystemVerilog monitor reconstructs bit-exact strings in zero simulated cycles (Δt_sim=0) using a build-time sidecar dictionary.
• The system is ISA-independent and requires zero firmware call-site edits, using a single header alias.
• Argument wire-slot encoding promotes narrow integers to 32-bit slots and serializes 64-bit values as two 32-bit words (low then high).
• Dynamic runtime strings are packed four characters per 32-bit word, terminated by a 0xFE sentinel.
• A post-link Python ELF dictionary extractor parses .rodata sections to create the sidecar dictionary.
• The SystemVerilog decoder uses a three-tier priority state machine for argument collection, token lookup, and legacy passthrough.

Implications

• Significant acceleration of full-chip RTL simulation, reducing overall verification time and resource consumption.
• Improved simulator throughput by reducing the evaluation cost of logging cycles.
• Reduced disk storage requirements for instruction traces, bus transaction logs, and waveform dumps.
• Exposure of latent multi-core firmware synchronization races due to the removal of artificial logging delays.
• The solution is portable across different CPU architectures (Arm, RISC-V, DSP) and compatible with standard toolchains.
• Maintains 100% live log visibility, crucial for UVM scoreboards and real-time pass/fail adjudication.

Limitations

• Evaluation relies on paired single-seed execution, with each test pair run once per configuration.
• Single-call parameters are measured from processor instruction traces, while whole-test savings are derived by dividing test-level runtime savings by print count.
• The evaluation compares against three specific production logging drivers, so absolute speedup magnitudes depend on the SoC's interconnect latency and workload print density.
• Shared-cluster wall-clock times are subject to host contention, affecting precise measurement of wall-clock savings.
• Some tests that passed in baseline but not under tokenization (due to environment timeouts and race-exposed tests) were excluded from the paired analysis.