ZynqParrot: A Scale-Down Approach to Cycle-Accurate, FPGA-Accelerated Co-Emulation

Abstract

ZynqParrot is an FPGA-accelerated co-emulation platform utilizing a novel "Scale-Down" approach for processor validation. This methodology decomposes large designs into manageable, independently prototyped sub-components, overcoming the cost and time limitations of traditional simulation and Scale-Up methods. The platform delivers non-interfering, cycle-accurate verification of arbitrary RTL designs, demonstrated via full-stack performance analysis of an open-source RISC-V processor.

Report

ZynqParrot: A Scale-Down Approach to Cycle-Accurate, FPGA-Accelerated Co-Emulation

Key Highlights

• Novel Methodology: Proposes the "Scale-Down" approach to modeling and validation, contrasting with traditional Scale-Up (expensive prototyping) and Scale-Out (inaccurate aggregation) methods.
• Platform: Introduces ZynqParrot, an FPGA-based platform designed specifically for this Scale-Down methodology.
• Core Capability: ZynqParrot is capable of executing non-interfering, cycle-accurate co-emulations of arbitrary RTL designs.
• Verification Speed: Aims to combine the high speed of FPGA acceleration with high accuracy, overcoming the dramatically long runtimes associated with deep microarchitectural simulation.
• Application: Successfully used to analyze the full-stack performance of an open-source RISC-V processor, verifying both functionality and performance.

Technical Details

• Scale-Down Principle: Rather than up-sizing prototyping platforms to fit large systems, the system is decomposed into manageable sub-components that are prototyped independently.
• Interface Design: Careful design of the prototyping interface is critical to adhere to strict non-interference protocols regarding the Device Under Test (DUT).
• Accuracy Granularity: The platform is capable of verifying functionality and performance with "arbitrary granularity."
• Target Domain: Focuses on processor verification, addressing the challenge of deeply inspecting core performance where typical silicon characterizations only offer aggregated performance counters.

Implications

• Improved Validation Quality: By enabling cycle-accurate, non-interfering co-emulation, ZynqParrot provides performance engineers with deep, trustworthy inspection capabilities previously hampered by the inaccuracy of Scale-Out or the slowness of pure simulation.
• Cost Efficiency in Hardware Design: The economical and faster nature of the Scale-Down approach reduces the rapid cost growth associated with verifying increasingly complex processors, making advanced validation accessible.
• Advancing RISC-V Ecosystem: The successful case study using ZynqParrot to analyze an open-source RISC-V processor signals a valuable new tool for the open hardware movement, facilitating robust verification and iteration of open-source CPU designs.
• Bridging the Gap: This platform effectively bridges the gap between fast, but often inaccurate, FPGA acceleration/emulation and slow, but accurate, microarchitectural simulation.