Zoozve: A Strip-Mining-Free RISC-V Vector Extension with Arbitrary Register Grouping Compilation Support (WIP)

Abstract

The Zoozve instruction extension addresses performance limitations in the standard RISC-V Vector Extension (RVV), specifically those caused by static register counts and required strip-mining for long vectors. Zoozve is a novel extension designed to eliminate strip-mining by introducing arbitrary register grouping and data-adaptive allocation. This innovation drastically cuts down instruction counts, demonstrated by a 10.10x reduction in dynamic instructions for FFT with minimal hardware overhead.

Report

Key Highlights

• Zoozve is a new RISC-V vector extension designed specifically to overcome performance restrictions associated with the static register count and power-of-two grouping limitations of the standard RVV.
• The core innovation is the elimination of the necessity for strip-mining, a technique traditionally required for handling very long vectors.
• The approach allows for arbitrary register groupings, leveraging a data-adaptive register allocation method.
• Initial results show a significant performance uplift, yielding a 10.10x reduction in dynamic instruction count for the Fast Fourier Transform (FFT).
• The hardware implementation is highly efficient, resulting in only a 5.2% increase in overall silicon area.

Technical Details

• Flexible Configuration: Zoozve allows for flexible vector register length and count configurations to boost data computation parallelism, moving beyond the fixed nature of RVV registers.
• Compilation Support: The extension includes comprehensive compilation support, utilizing LLVM for the compiler implementation.
• Hardware Implementation: The hardware architecture is detailed and implemented using SystemVerilog.
• Optimization Strategy: The adaptive allocation method accurately aligns vector lengths, aiming to reduce register overhead and alleviate performance declines caused by mandated strip-mining in standard RVV.

Implications

• Performance for Data-Parallel Tasks: By drastically reducing dynamic instruction counts and eliminating strip-mining overhead, Zoozve promises major performance gains for crucial data-parallel algorithms like signal processing and potentially AI workloads.
• Architectural Advancement: This work proposes a significant architectural refinement to the RISC-V vector paradigm, addressing fundamental limitations that restrict scaling for long-vector applications.
• Ecosystem Readiness: The availability of implementations in key industry tools (LLVM for software and SystemVerilog for hardware) suggests a mature and immediately actionable proposal for the RISC-V ecosystem.
• Efficiency Benchmark: Achieving a massive performance gain (10.10x instruction reduction) while keeping area overhead low (5.2%) establishes a highly compelling case for integrating this extension.