X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller for the Exploration of Ultra-Low-Power Edge Accelerators

Abstract

X-HEEP (eXtendible Heterogeneous Energy-Efficient Platform) is an open-source, configurable RISC-V microcontroller designed to natively support and accelerate the integration of custom ultra-low-power edge accelerators. The platform offers extensive customization options, including variable core types, bus topologies, and memory sizes, while prioritizing efficiency through strategies like clock-gating and power-gating. Its application, HEEPocrates, demonstrated substantial energy benefits, achieving up to 4.9x greater efficiency by exploiting integrated accelerators (CGRA and IMC) compared to running tasks solely on the host CPU.

Report

Key Highlights

• X-HEEP Platform: Introduction of an open-source, highly configurable RISC-V microcontroller platform optimized for ultra-low-power edge computing applications.
• Extensibility Focus: Specifically designed to overcome limitations in existing platforms by natively supporting the integration and exploration of custom, specialized heterogeneous accelerators.
• Energy Efficiency: Prioritizes low-power operation through the implementation of advanced strategies, notably clock-gating and power-gating.
• Proven Gains: Demonstrated energy benefits of 4.9x and 4.8x when utilizing the integrated coarse-grained reconfigurable array (CGRA) and in-memory computing (IMC) accelerators, respectively, versus executing the same tasks on the host CPU.
• Real-World Example: The platform was validated through a tailored integration called HEEPocrates, targeting healthcare applications.

Technical Details

• Architecture Base: A RISC-V microcontroller serving as the host processor within a heterogeneous architecture.
• Configuration Points: Supports customization across multiple architectural layers, including exploration of various core types, bus topologies, addressing modes, memory sizes, and peripheral sets.
• Implemented Accelerators (in HEEPocrates): Integration included both a Coarse-Grained Reconfigurable Array (CGRA) and an In-Memory Computing (IMC) accelerator.
• Fabrication and Validation: The design was implemented in Field Programmable Gate Array (FPGA) on the Xilinx Zynq-7020 chip and fabricated in silicon using TSMC 65nm low-power CMOS technology.
• Power Optimization: Energy-saving techniques include aggressive use of clock-gating and power-gating.

Implications

• Democratization of Heterogeneous Computing: By being open-source and highly extendible, X-HEEP significantly lowers the barrier to entry for researchers and developers wishing to prototype and deploy custom RISC-V edge accelerators.
• Accelerating Edge AI/IoT: The demonstrated energy efficiency gains (up to 4.9x) confirm the necessity and effectiveness of heterogeneous integration for pushing computational capabilities into severely power-constrained edge devices (e.g., wearables and medical IoT).
• RISC-V Ecosystem Growth: X-HEEP contributes a validated, flexible, and energy-focused reference platform, encouraging the development of specific RISC-V instruction set extensions and accelerator IP focused on ultra-low-power domains, thus strengthening the RISC-V ecosystem's position in specialized markets.