Wildcat: Educational RISC-V Microprocessors

Abstract

The paper "Wildcat" challenges the traditional 5-stage pipeline model used in computer architecture education by examining simpler RISC-V organizations for teaching and implementation. Analysis across FPGA and SkyWater130 ASIC designs revealed that longer pipelines (4 or 5 stages) often result in slower maximum clock frequencies than a 3-stage design. This counter-intuitive performance degradation is attributed to the increased width and complexity of the forwarding multiplexer, leading the author to recommend the 3-stage architecture for its pedagogical clarity and physical efficiency.

Report

Wildcat: Educational RISC-V Microprocessors Report

Key Highlights

• Educational Challenge: The paper addresses the reliance on the traditional, potentially suboptimal, five-stage pipeline for teaching computer architecture, proposing simpler alternatives.
• Empirical Finding: Contrary to common industry wisdom, implementing a longer pipeline (four or five stages) did not consistently increase the maximum clock frequency compared to a three-stage design in specific FPGA and ASIC implementations.
• Critical Path Identified: The performance bottleneck for longer pipelines was found to be the widening of the forwarding multiplexer within the execution stage, which limits the clock speed.
• Recommendation: The 3-stage pipeline organization is argued to be more adequate and effective for both teaching microprocessor organization and for efficient resource utilization in embedded hardware.

Technical Details

• Architecture Focus: Simplistic pipeline organizations for RISC processors, optimized for educational purposes and implementation in FPGAs and ASICs.
• Methodology: Resource costs and maximum clock frequency (used as a performance proxy) were analyzed for various pipeline lengths.
• Implementation Platforms: Designs were implemented and tested on commercial FPGAs. Results were validated through ASIC synthesis using the open-source SkyWater130 (Sky130) process.
• Observed Results: In two FPGA tests and one ASIC synthesis, the three-stage implementation demonstrated a faster clock frequency than the four- or five-stage implementations.

Implications

• Pedagogical Shift: The research provides strong evidence supporting the use of the 3-stage pipeline as the foundational model in computer architecture courses, offering a simpler representation of pipeline organization without sacrificing realism.
• Efficient RISC-V Implementation: For developers targeting low-cost, resource-constrained environments (like embedded FPGAs or basic ASICs using open-source processes like Sky130), this work suggests that optimizing for pipeline length beyond three stages may be counterproductive to achieving high clock speed.
• Hardware Design Principle: It emphasizes that the complexity of control logic (specifically forwarding mechanisms) can become the ultimate limiter of pipeline performance, overshadowing the benefits of increased stage parallelism, particularly in small core designs.