WebRISC-V: A 64-bit RISC-V Pipeline Simulator for Computer Architecture Classes

Abstract

WebRISC-V is a new web-based educational simulator designed to visualize the pipelined execution of 64-bit RISC-V assembly programs, adhering to the RV64IM specification. The tool allows users to inspect the internal state of architectural blocks and observe cycle-by-cycle instruction flow, specifically aiding in the investigation of pipeline stalls. By executing directly in a web browser, WebRISC-V offers an accessible platform for teaching complex computer architecture concepts.

Report

WebRISC-V: A 64-bit RISC-V Pipeline Simulator Analysis

Key Highlights

• Web-Based Accessibility: WebRISC-V is implemented as a tool that executes directly within a standard web browser, eliminating local setup complexity for users.
• Educational Focus: The simulator is explicitly designed as an educational tool for computer architecture classes.
• 64-bit Simulation: It supports the full 64-bit RISC-V processor specification.
• Pipeline Visualization: The primary feature is the ability to visualize the complex, cycle-by-cycle execution of assembly instructions through the pipeline stages.
• Stall Investigation: Users can specifically investigate and understand the mechanisms behind pipeline stalls and hazards.

Technical Details

• Architecture Standard: Simulates the pipelined execution model.
• Instruction Set Specification: Adheres to the RV64IM specification (RISC-V 64-bit with Integer, Multiplication, and Division instructions).
• Execution Insight: Provides detailed visibility into the internal state of pipeline architectural blocks.
• Input/Output: Processes assembly programs and displays the resultant pipeline flow and state updates.

Implications

• Lowering Barriers to Education: The web-based implementation significantly lowers the barrier to entry for students, enabling hands-on learning of advanced architecture topics without relying on specific operating systems or powerful local machines.
• RISC-V Academic Adoption: By providing a high-quality, specialized teaching tool, WebRISC-V reinforces the adoption and integration of the RISC-V architecture into university curricula globally.
• Improved Conceptual Understanding: The visualization of pipeline stalls and internal states helps students grasp inherently difficult timing and dependency concepts, leading to a deeper understanding necessary for designing future hardware and optimizing software.