vlang: Mapping Verilog Netlists to Modern Technologies

Abstract

This paper introduces vlang, a novel framework designed to solve the challenge of migrating device-specific Verilog netlists to modern computational targets when original design files are unavailable. vlang automatically translates these netlists into LLVM's Intermediate Representation (IR), overcoming restrictions imposed by device-specific primitives. This LLVM IR output enables seamless portability across diverse architectures, including RISC-V, x86-64, and ARM, while preserving the exact, cycle-accurate functionality of the original hardware design.

Report

Key Highlights

• Core Innovation (vlang): A new framework designed to map device-specific Verilog netlists into a technology-agnostic representation.
• Portability Solution: Addresses the loss of design portability when only low-level, primitive-dependent netlists are available.
• Target Output: The framework translates Verilog netlists directly into LLVM Intermediate Representation (IR).
• Broad Targeting: The resulting design can be compiled using the LLVM ecosystem to target a wide range of devices, including standard CPUs (x86-64, ARM), microprocessors ($\mu$P), GPGPUs, and specific architectures like RISC-V.
• Functionality Preservation: vlang produces a fully-functional, cycle-accurate software executable of the original hardware design.
• Evaluation: The framework was tested using a suite of complex hardware designs sourced from OpenCores and compared favorably against state-of-the-art simulators.

Technical Details

• Input Format: Verilog-netlists, specifically those containing device-specific primitives typically recovered through reverse engineering.
• Translation Process: vlang acts as a front-end, automatically interpreting the netlist structure and mapping it into the high-level LLVM IR.
• Target Use Cases: The LLVM IR can be used for two primary purposes: 1) generating traditional software executables for simulation and verification, and 2) acting as a front-end input for modern High-Level Synthesis (HLS) tools to re-target the design to alternative PLDs.
• Verification Output: The generated software executable serves as a cycle-accurate model, allowing for verification and correctness checks of the remapped design against the original specification.

Implications

• Enhancing RISC-V Adoption: By translating existing legacy or proprietary hardware logic (captured only as netlists) into LLVM IR, vlang significantly lowers the barrier to integrating these blocks into modern RISC-V based System-on-Chips (SoCs). This supports the migration of established IP to open architectures.
• Design Migration and Preservation: This work ensures that recovered or aged hardware designs are not restricted to obsolete or specific PLD vendors. It enables modernization by porting functionality to general-purpose computing platforms or advanced process nodes via HLS tools.
• Hardware/Software Co-Design and Simulation: The ability to generate a cycle-accurate software executable facilitates rapid high-performance simulation and functional verification. This accelerates hardware/software co-design workflows by allowing the hardware logic to be run alongside traditional software programs on standard CPUs (like x86 or RISC-V).
• Technology Agnosticism: By utilizing LLVM IR, vlang leverages a robust, industry-standard optimization and compilation framework, decoupling the design logic from the underlying fabrication or target technology.