vCLIC: Towards Fast Interrupt Handling in Virtualized RISC-V Mixed-criticality Systems

vCLIC: Towards Fast Interrupt Handling in Virtualized RISC-V Mixed-criticality Systems

Abstract

The paper introduces vCLIC, a novel hardware virtualization extension for the RISC-V Core Local Interrupt Controller (CLIC), designed to enhance performance in virtualized mixed-criticality systems. Addressing the limitations of current non-deterministic MSI and slow software emulation, vCLIC integrates essential real-time features like vectoring and nesting directly into the hardware. This extension achieves a significant 20x interrupt latency speed-up over software emulation and reduces response latency by 15% compared to bus-mediated MSI approaches.

Report

Key Highlights

  • Core Innovation: Introduction of vCLIC, a virtualization extension specifically designed for the RISC-V Core Local Interrupt Controller (CLIC).
  • Performance Gain (Software Emulation): Achieves a 20x speed-up in interrupt latency compared to the required software emulation for handling non-virtualization-aware systems.
  • Performance Gain (MSI): Reduces interrupt response latency by 15% compared to existing Message-Signaled Interrupt (MSI)-based virtualization approaches.
  • Determinism: The vCLIC approach is explicitly free from interference from the system bus, ensuring better real-time determinism.
  • Target Applications: Designed for advanced heterogeneous embedded architectures supporting compute-intensive edge-AI workloads and stringent autonomous systems.

Technical Details

  • Base Controller: Extends the existing RISC-V CLIC (Core Local Interrupt Controller).
  • Feature Support: The design maintains crucial real-time system features under virtualization, including interrupt vectoring, nesting, and tail-chaining, ensuring transparency to virtual guests.
  • Comparison to Legacy: Addresses the current RISC-V reliance on non-deterministic, bus-mediated MSIs for interrupt virtualization.
  • Implementation Overhead: The hardware extension requires a minimal area cost of just 8kGE (Gate Equivalents) when synthesized in an advanced 16nm FinFet technology.

Implications

  • Enables Mixed-Criticality Systems: vCLIC is crucial for isolating high-performance and safety-critical applications executing concurrently under real-time constraints, which is vital for autonomous vehicles and industrial control systems.
  • Advancement of RISC-V Virtualization: Solves a major architectural challenge in the RISC-V ecosystem by providing the missing link—an interrupt controller with integrated hardware virtualization and robust real-time features.
  • Improved QoS and Reliability: By eliminating reliance on slow software emulation and non-deterministic bus-mediated MSIs, vCLIC ensures significantly faster and more predictable interrupt handling, improving the overall Quality of Service (QoS) for real-time applications.
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