Unlimited Vector Processing for Wireless Baseband Based on RISC-V Extension

Abstract

This paper introduces the Unlimited Vector Processing (UVP) instruction set extension for RISC-V, specifically targeting performance improvements in wireless baseband processing (WBP). UVP overcomes conventional vector architecture constraints by implementing a novel programming model that supports non-power-of-two register groupings and hardware strip-mining for flexible vector length handling. Comprehensive evaluations demonstrate significant performance gains, achieving speedups of up to 3.0x for matrix multiplication and 2.1x for Fast Fourier Transform (FFT) tasks.

Report

Key Highlights

• Core Innovation: Introduction of the Unlimited Vector Processing (UVP) instruction set extension based on RISC-V.
• Target Application: Optimized specifically for Wireless Baseband Processing (WBP), a highly data-parallel workload.
• Flexibility Improvement: UVP removes constraints found in conventional architectures, such as limited vector register size and reliance on power-of-two vector length multipliers.
• Performance Metrics: Achieves substantial speedups compared to lane-based vector architectures: up to 3.0x for matrix multiplication and 2.1x for FFT.
• Hardware Efficiency: The synthesized 16-lane RTL core (using SMIC 40nm technology) occupies 0.94 mm² and boasts an impressive area efficiency of 21.2 GOPS/mm².

Technical Details

• Programming Model: UVP employs a novel approach supporting non-power-of-two register groupings and integrated hardware strip-mining, which significantly reduces the burden of software strip-mining.
• Instruction Classes: Vector instructions are categorized into symmetric and asymmetric classes to optimize execution flow.
• Data Handling: Specialized load/store strategies are implemented to complement vector operations and maximize efficiency.
• Hardware Implementation Features: The core UVP hardware includes sophisticated hazard detection mechanisms and optimized pipelines specifically designed for symmetric tasks, such as fixed-point multiplication and division.
• Permutation Engine: A robust permutation engine is utilized to effectively handle complex asymmetric operations.

Implications

• RISC-V Specialization: UVP demonstrates the powerful extensibility of the RISC-V architecture, allowing developers to create highly specialized, high-performance instruction sets perfectly tailored for demanding domains like wireless signal processing.
• Market Competitiveness: By effectively addressing the limitations of fixed-length vector processing common in traditional DSPs, this extension makes RISC-V a stronger competitor in the critical 5G/6G base station and communication hardware markets.
• Efficiency Benchmark: The high performance gains coupled with the reported area efficiency (21.2 GOPS/mm²) suggest UVP is a viable and practical solution for high-throughput, low-power embedded systems.
• Future Vector Development: The use of hardware strip-mining and flexible vector grouping provides a blueprint for future vector architecture designs seeking to simplify compiler optimization and enhance utilization on variable-length datasets.