Abstract

The Trikarenos design is a fault-tolerant, 28nm RISC-V System-on-Chip developed for demanding automotive and space applications, incorporating Error Correction Codes (ECC) and Triple-Core Lockstep (TCLS) mechanisms. This study experimentally characterizes the fabricated SoC under controlled neutron and proton radiation to quantify its resilience against Single Event Upsets (SEUs). Results validate the high fault tolerance, showing TCLS effectively corrects errors up to a cross-section of $3.23 \times 10^{-11}$ cm$^2$ and achieves 100% successful error handling during gate-level fault injection simulations.

Report

Trikarenos: Design and Experimental Characterization of a Fault-Tolerant 28nm RISC-V-based SoC

Key Highlights

• Design Focus: Trikarenos is a fault-tolerant RISC-V SoC explicitly designed for safety-critical systems, such as next-generation automotive and space architectures.
• Manufacturing Node: The SoC was implemented and fabricated using TSMC 28nm technology.
• Primary Protection Mechanisms: It employs Triple-Core Lockstep (TCLS) for CPU redundancy and Error Correction Codes (ECC) protected memory augmented by a dedicated scrubber.
• Validation Method: The design was experimentally characterized by subjecting fabricated chips to controlled radiation environments (atmospheric neutron and 200 MeV proton radiation).
• High Reliability: Gate-level fault injection simulations demonstrated exceptional fault coverage, resulting in 99.10% of all injections into the SoC producing correct results, and 100% of injections within the TCLS-protected cores being handled correctly.

Technical Details

• Core Fault Tolerance: The TCLS mechanism was experimentally validated, demonstrating its ability to correct errors corresponding to a cross-section up to $3.23 \times 10^{-11}$ cm$^2$.
• Uncorrectable Vulnerability: The remaining uncorrectable vulnerability after TCLS mitigation was quantified to be exceptionally low, below $5.36 \times 10^{-12}$ cm$^2$.
• Memory Fault Tolerance: ECC-protected memory, combined with the scrubber, successfully corrected all observed faults, exhibiting an estimated cross-section per bit of up to $1.09 \times 10^{-14}$ cm$^2$ bit$^{-1}$.
• Simulation Metrics: Fault injection analysis indicated that 12.28% of all injected faults specifically triggered a TCLS recovery event. This led to an approximate effective flip-flop cross-section of up to $1.28 \times 10^{-14}$ cm$^2$/FF.
• Test Conditions: Reliability assessment involved characterization under high-energy radiation (atmospheric neutrons and 200 MeV protons) to simulate real-world Single Event Upset (SEU) conditions.

Implications

• Maturity of RISC-V for Critical Systems: The Trikarenos project provides critical, measurable proof that complex fault-tolerant methodologies (TCLS, ECC) can be successfully integrated into commercial RISC-V architectures using mainstream semiconductor nodes (28nm).
• Benchmark for Space/Automotive Qualification: The precise quantification of cross-section vulnerabilities under proton and neutron irradiation provides essential data necessary for qualifying RISC-V based SoCs for demanding aerospace and functional safety (ASIL-D) standards.
• Validation of TCLS Efficacy: The 100% fault-handling success rate observed in the TCLS-protected cores during simulation strongly validates this redundancy technique as a robust strategy for protecting processor cores against radiation-induced transient faults.
• Methodological Advancement: By comparing physical radiation testing results with simulation-based fault injection, the study helps validate and refine design-time verification tools, improving the efficiency of developing future high-reliability silicon.