Trikarenos: A Fault-Tolerant RISC-V-based Microcontroller for CubeSats in 28nm

Trikarenos: A Fault-Tolerant RISC-V-based Microcontroller for CubeSats in 28nm

Abstract

Trikarenos is a fault-tolerant, 32-bit RISC-V microcontroller SoC fabricated in an advanced TSMC 28nm technology, specifically designed to mitigate radiation-induced Single Event Upsets (SEUs) in harsh space environments like CubeSats. Its key innovation is a configurable architecture utilizing three Ibex cores that can run either in triple-core lockstep for maximum reliability or independently in parallel for peak performance and efficiency. This approach yields a 21.5x efficiency gain over existing state-of-the-art solutions while offering dynamic performance scaling when fault tolerance is not required.

Report

Key Highlights

  • Advanced Technology for Space: Trikarenos successfully implements a radiation-tolerant design using a commercial advanced node (TSMC 28nm), challenging the reliance on low-density or proprietary radiation-hardened technologies.
  • Configurable Redundancy: The system features a unique configurable architecture that allows switching between high-reliability mode (triple-core lockstep) and high-performance parallel mode.
  • RISC-V Foundation: The SoC is built around the open-source 32-bit RISC-V instruction set, leveraging Ibex cores.
  • Exceptional Efficiency: In the fault-tolerant mode, the design demonstrates a 21.5x efficiency gain executing a matrix-matrix multiplication compared to current state-of-the-art systems.
  • Target Application: Primarily intended for CubeSats and other small satellite missions operating in radiation-prone orbits.

Technical Details

Specification Detail
Microcontroller Type 32-bit RISC-V SoC
Cores Used Three Ibex cores
Fabrication Process TSMC 28nm technology
Primary Threat Addressed Radiation-induced Single Event Upsets (SEUs)
Fault Tolerance Mechanism Configurable Triple-Core Lockstep (TCL) configuration
Memory Protection ECC-protected memory
Power Consumption (TCL Mode) 15.7mW
Operating Frequency (TCL Mode) 250MHz
Performance Gain (Parallel Mode) 2.96x performance increase
Efficiency Gain (Parallel Mode) 2.36x energy efficiency increase

Implications

For the RISC-V Ecosystem:

  1. Validation in Critical Applications: Trikarenos provides robust proof that open-source RISC-V cores (specifically Ibex) can be utilized effectively in highly specialized, safety-critical environments like space where traditional radiation-hardened architectures have historically dominated.
  2. Architectural Innovation over Process Reliance: This work shifts the focus from relying solely on expensive, high-cost rad-hard manufacturing processes to clever architectural solutions (TCL, configurable modes) on commodity nodes, expanding the potential market for RISC-V in specialized computing.
  3. Flexibility and Efficiency: The configurable nature of the design—allowing users to dynamically trade off reliability for performance—is crucial for CubeSat missions, where power budgets are tight but processing demands vary greatly between mission phases (e.g., launch, deployment, payload processing). This maximizes the utility of the hardware platform.

For the Tech Ecosystem:

  • Lowering Barriers to Space Access: By using a standard 28nm process, Trikarenos promises significantly reduced production costs compared to traditional solutions, making advanced onboard computing more accessible for small satellite development.
  • High-Density Computing in Space: Utilizing a 28nm process allows for higher transistor density and better performance/power ratios than previous generations of space-hardened electronics, enabling more sophisticated processing tasks for CubeSats.
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