Towards Base-Station-On-Chip: Wireless Communication Kernels On A RISC-V Vector Processor (TU Dresden, CeTI) - Semiconductor Engineering

Abstract

Researchers from TU Dresden's Center for Tactile Internet (CeTI) are investigating the potential of the RISC-V Vector Processor to efficiently handle demanding wireless communication kernels. This research aims to prove the feasibility of implementing entire cellular base station functionality onto a single system-on-chip (SoC), known as a Base-Station-On-Chip (BS-o-C). The successful execution of these parallel workloads on RISC-V Vector extensions could significantly advance open-standard hardware adoption in 5G and future wireless infrastructure.

Report

Key Highlights

• Goal: Development of a highly integrated 'Base-Station-On-Chip' (BS-o-C) solution, drastically reducing the physical footprint and power consumption of wireless infrastructure.
• Target Workload: Critical wireless communication kernels, which require significant parallel processing capabilities (e.g., FFTs, channel coding, equalization).
• Enabling Technology: Utilization of the RISC-V Instruction Set Architecture (ISA), specifically leveraging the Vector extension (RVV) for data-parallel acceleration.
• Affiliation: Research conducted by TU Dresden, specifically affiliated with the CeTI (Center for Tactile Internet), signaling a focus on low-latency, high-throughput applications.

Technical Details

• Architecture Focus: The study concentrates on mapping complex Digital Signal Processing (DSP) tasks—the core of physical layer processing in cellular systems (like 5G)—onto the general-purpose, yet extensible, RISC-V core.
• Vector Processing Necessity: Wireless kernels are inherently parallel, requiring Single Instruction, Multiple Data (SIMD) capabilities. The RISC-V Vector extension (RVV) is the mechanism used to efficiently handle large data vectors associated with signal processing without relying on fixed-function accelerators.
• Kernel Implementation: The research involves optimizing, scheduling, and potentially micro-architecturally customizing the RISC-V vector unit to maximize throughput and minimize latency for crucial wireless processing blocks.
• Comparison Implicit: The work implicitly compares the performance, efficiency, and flexibility of a vector-enabled RISC-V implementation against traditional solutions, such as specialized DSPs or FPGAs typically used in commercial base stations.

Implications

• RISC-V Validation in Infrastructure: This project serves as crucial validation that RISC-V is capable of handling heavy computational loads required by wireless infrastructure, a domain often restricted to proprietary architectures (like specialized x86/ARM embedded cores or dedicated DSP silicon).
• Democratization of Telecom Hardware: By utilizing an open ISA like RISC-V, this research contributes to the broader movement towards Open RAN and highly flexible, vendor-agnostic telecom solutions.
• Vector Extension Proving Ground: Successfully implementing demanding communication kernels highlights the maturity and effectiveness of the RISC-V Vector extension (RVV) for real-world domain-specific acceleration (DSA).
• Future Wireless (6G): Establishing RISC-V as a viable platform for BS-o-C solutions is foundational for future wireless standards (6G), which will demand even greater energy efficiency and processing density.