Toward Comprehensive Design Space Exploration on Heterogeneous Multi-core Processors

Abstract

Designing optimal heterogeneous multi-core processors requires navigating an exponentially large Design Space Exploration (DSE) covering core mixes, interconnects, and scheduling policies. This paper introduces a novel, comprehensive DSE framework specifically tailored for highly configurable architectures, such as those based on RISC-V. By integrating hierarchical pruning techniques and efficient performance modeling, the methodology significantly reduces exploration time while ensuring the identification of optimized hardware/software co-designs across PPA metrics.

Report

Technical Report: Toward Comprehensive Design Space Exploration on Heterogeneous Multi-core Processors

Key Highlights

• Addressing DSE Complexity: The work tackles the primary challenge of rapidly growing design complexity in heterogeneous multi-core systems (combining performance, efficiency, and accelerator cores).
• Novel Hierarchical Methodology: The core innovation is a hierarchical DSE framework that uses coarse-grained analytical models to prune the majority of suboptimal designs before employing resource-intensive, cycle-accurate simulation.
• PPA Optimization: The research demonstrates success in finding superior Pareto frontiers for Power, Performance, and Area (PPA) trade-offs, often locating optimal designs missed by traditional, limited DSE strategies.
• Scalability Demonstrated: The framework proved scalable, enabling the comprehensive evaluation of design spaces previously considered intractable due to the combination of numerous core types and memory hierarchy configurations.

Technical Details

• Target Architecture: Focuses on standard asynchronous heterogeneous multi-core System-on-Chip (SoC) architectures, where specialized processing elements (P-cores, E-cores, DSPs) communicate via a Non-Uniform Cache Access (NUCA) interconnect.
• Exploration Method: A two-stage DSE process:
  1. Analytical Pruning (Stage 1): Utilizes fast functional models and statistical learning (e.g., Gaussian Process Regression) to quickly estimate PPA bounds and filter out configurations that violate performance or power targets.
  2. Detailed Validation (Stage 2): Applies cycle-accurate simulation only to the reduced set of promising configurations to achieve precise performance metrics and validate system behavior.
• Metrics: Emphasis on co-optimization metrics, including energy-delay product (EDP) and total area budget constraints, measured across standard benchmark suites (e.g., PARSEC, specialized RISC-V workloads).
• Configurable Parameters: Explores configurations involving core counts (up to 32 cores), L1/L2 cache sizes, coherence protocols, and scheduling policies (e.g., thread migration thresholds).

Implications

• Enabling RISC-V Customization: This methodology is critical for the RISC-V ecosystem. Since RISC-V’s primary strength is its extensibility and custom instruction set support, the sheer number of configuration permutations is massive. This DSE solution makes designing customized, application-specific RISC-V processors feasible and economically viable.
• Reduced Time-to-Market: By drastically cutting the time required to evaluate optimal SoC configurations (potentially from months to days), the framework accelerates the design cycle for commercial RISC-V implementers.
• Advancement in Tooling: The paper contributes essential advanced architectural tooling necessary for large-scale industrial use. Efficient DSE tools move RISC-V development beyond simple core instantiation toward sophisticated, production-ready system co-design.
• Optimized Resource Use: By reliably finding points closer to the theoretical Pareto frontier, designers can achieve required performance with minimal power draw and silicon area, crucial for competitive embedded and datacenter applications.