TOP: Towards Open & Predictable Heterogeneous SoCs

Abstract

The TOP methodology addresses the critical challenge of ensuring predictability in heterogeneous real-time SoCs by leveraging the rise of open-source hardware (RISC-V) to facilitate comprehensive architectural analysis. This approach models and analyzes the entire set of open-source IPs, including interconnects and shared memory, which are typically closed-source barriers to predictability modeling. Validated on a low-power RISC-V architecture, TOP significantly minimizes the pessimism in bounding transaction service times, achieving a reduction between 28% and 1% compared to prior art.

Report

Key Highlights

• Goal: To establish predictability in modern real-time Systems-on-Chip (SoCs) essential for applications like robotics, automotive, and industrial automation.
• Innovation (TOP): An innovative methodology for comprehensively modeling and analyzing State-of-the-Art (SoA) open-source SoCs, overcoming limitations of analyzing closed-source single modules.
• Target Architectures: Heterogeneous, low-power RISC-V systems designed for cyber-physical applications.
• Performance Result: The methodology validated on a sample RISC-V architecture minimized pessimism in bounding transaction service time to between 28% and 1%, significantly outperforming similar published works.
• Approach: Focuses on modeling the entire set of open-source IPs (including interconnects and memory resources) rather than just isolated components.

Technical Details

• Problem Addressed: The difficulty in evaluating deterministic behavior in real-time SoCs due to proprietary, closed-source Intellectual Property (IP) for critical components like interconnects and shared memory.
• Modeling Scope: The methodology models and analyzes the full architecture of open-source SoCs, specifically targeting low-power designs.
• Validation Methods: The approach was validated using both Register Transfer Level (RTL) simulation and FPGA implementation.
• Testbed: A sample heterogeneous low-power RISC-V architecture was used to demonstrate the technique.
• Metric: Success was quantified by the minimization of pessimism when calculating the bound on the service time required for transactions crossing the architecture.

Implications

• Advancing RISC-V in Safety-Critical Domains: TOP demonstrates how the open nature of RISC-V and related hardware can be utilized to achieve the strict predictability and timing guarantees necessary for safety-critical applications (e.g., autonomous systems).
• Increased Trust in Open Hardware: By providing highly accurate and less pessimistic Worst-Case Execution Time (WCET) bounds, this work significantly increases the reliability and trustworthiness of open-source hardware designs for real-time systems.
• Breaking Vendor Lock-in: The ability to model and analyze full SoCs removes reliance on proprietary vendor information regarding interconnect and memory arbitration, fostering deeper architectural innovation in the open-source ecosystem.
• Foundation for Future CPS: This methodology provides a crucial tool for engineers developing the next generation of complex cyber-physical systems, where low-power operation must coexist with stringent timing determinism.