The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V

Abstract

This paper renews the argument for Reduced Instruction Set Computers (RISC), demonstrating that the open RISC-V ISA, particularly its compressed variant (RV64GC), can achieve performance and code density superior to complex proprietary ISAs like x86-64. The central innovation is leveraging microarchitectural macro-op fusion to combine common multi-instruction sequences, effectively reducing the dynamic instruction count by 5.4% without adding complexity to the ISA. This strategy maintains the core simplicity of RISC-V while providing performance boosts traditionally associated with complex instruction sets, successfully avoiding ISA bloat.

Report

Key Highlights

• Code Density Leadership: The compressed RISC-V variant (RV64GC) was the densest Instruction Set Architecture (ISA) studied, fetching 8% fewer dynamic instruction bytes than the highly optimized x86-64 ISA.
• Instruction Count Parity with Micro-ops: While the standard RV64G executes 16% more instructions than x86-64, its instruction count is statistically equivalent (within 2%) of the retired micro-op count of x86-64 implementations.
• Macro-Op Fusion Efficacy: By applying macro-op fusion—a microarchitectural technique—to common multi-instruction idioms, the effective dynamic instruction count of RISC-V was reduced by 5.4% on average.
• Avoiding ISA Bloat: The combination of the compressed ISA extension (RV64GC) and macro-op fusion successfully provides both the highest code density and the lowest number of dynamic operations retired, removing the pressure to add complex instructions to the base RISC-V specification.

Technical Details

• ISAs Evaluated: The study compared dynamic instruction counts and dynamic instruction bytes fetched for proprietary ISAs (ARMv7, ARMv8, IA-32, x86-64) against the open ISAs RISC-V RV64G and RV64GC.
• Benchmark: All comparisons were conducted using the standard SPEC CINT2006 benchmark suite.
• RV64G Performance Baseline: RV64G instruction count results showed a 16% increase compared to x86-64, a 9% increase over ARMv8, a 3% increase over IA-32, but a 4% decrease compared to ARMv7.
• Methodology: The paper identifies that the instruction count discrepancy is largely caused by frequent, predictable multi-instruction idioms in RISC-V code. Macro-op fusion exploits this by merging these short sequences into a single internal micro-op during execution.
• Goal: To show that complex functionality can be handled via microarchitectural innovation (fusion) in high-end implementations, preserving the basic simple ISA for low-end implementations.

Implications

• Reinforcement of RISC Design Principles: This work strongly validates the original RISC philosophy. It demonstrates that performance and density gains typically achieved by CISC instruction complexity can be met or exceeded through simple instruction sets combined with clever microarchitectural optimization.
• Strengthening RISC-V's Competitiveness: The findings prove that RISC-V can compete directly against established commercial architectures like ARM and x86 in terms of density and operational efficiency, giving the open ISA a significant technological advantage.
• Future ISA Stability: By offering a clear path for performance scaling (macro-op fusion) that does not require ISA extensions, the research safeguards RISC-V against the historical "ISA bloat" that plagued older architectures like x86.