The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes

Abstract

This paper presents the microarchitecture of an open-source, multi-threaded processing core family designed for low-power Internet-of-Things (IoT) end-nodes. The core is fully compliant with the RISC-V instruction set and maintains hardware compatibility with the popular Pulpino platform. A key innovation introduced is the novel implementation of interleaved multi-threading, which efficiently handles the concurrent control threads demanded by heterogeneous IoT architectures.

Report

Key Highlights

• Target Domain: The core family is specifically designed for low-power IoT end-nodes that require heterogeneous dedicated units and concurrent control thread execution.
• RISC-V Compliance: The processor is compliant with the RISC-V instruction set on the software side.
• Hardware Foundation: The architecture is designed to be compatible with the existing, popular open-source Pulpino processor platform.
• Core Innovation: The primary novel contribution is the inclusion of interleaved multi-threading, optimized for IoT application demands.
• Open Source: The processing core is released as an open-source project.

Technical Details

• Architecture Focus: Addresses the need for platforms capable of running concurrent control threads across heterogeneous dedicated units, which is characteristic of modern IoT platforms.
• Multi-threading Mechanism: Implements interleaved multi-threading, an execution model suitable for latency hiding in environments where threads frequently stall waiting for external events or I/O, common in IoT.
• Reported Data: The paper includes detailed reports covering the microarchitecture design specifications and measured performance data, validating the approach.
• Platform Integration: Ensures compatibility with the well-established Pulpino ecosystem, simplifying adoption for developers already utilizing that hardware environment.

Implications

• Advancing RISC-V in IoT: This work validates RISC-V as a suitable ISA for highly specialized, power-constrained application domains like IoT, specifically addressing the requirement for concurrency.
• Increased Efficiency for IoT Workloads: Interleaved multi-threading is critical for enhancing utilization and responsiveness in IoT devices, where control flow involves frequent interaction with sensors and actuators (I/O heavy tasks).
• Ecosystem Growth: Providing an open-source, multi-threaded core compatible with a known platform (Pulpino) lowers the barrier to entry for developers wishing to implement custom RISC-V solutions for complex IoT tasks.
• Standardized Approach to Heterogeneity: The design caters directly to heterogeneous architectures, setting a standard for how RISC-V processors can manage parallel control over dedicated IP blocks in energy-efficient systems.