Abstract

This paper presents a thorough energy and performance analysis of Ariane, an open-source, single-issue 64-bit RISC-V core implemented for application-class processing and supporting the Linux OS. Taped-out in 22nm FDSOI technology, the core achieves speeds up to 1.7 GHz and demonstrates peak efficiency of 40 Gop/sW through silicon measurements and calibrated simulation. The analysis quantifies the energy cost of features required for Linux execution, indicating that targeted ISA extensions like packed SIMD are necessary to significantly boost compute energy efficiency.

Report

Key Highlights

• Application-Class Validation: The study validates the power, performance, and efficiency of the Ariane core, an open-source RISC-V implementation designed for baseline application-class functionality (i.e., supporting the Linux OS).
• High Frequency Achieved: The taped-out silicon instance runs at a competitive frequency of up to 1.7 GHz.
• Energy Efficiency: The implementation achieves a peak compute efficiency of up to 40 Gop/sW.
• Technology Focus: The core was implemented and measured in GlobalFoundries 22 FDX (22nm FDSOI) technology.
• Core Conclusion: Analysis shows that standard application requirements (like virtual memory) impose significant energy costs, and suggests ISA heterogeneity and specific instruction extensions (e.g., packed SIMD) are key to efficiency gains.

Technical Details

• Core Implementation: Ariane, an open-source implementation of the 64-bit RISC-V Instruction Set Architecture (ISA).
• Architecture: Single-issue in-order pipeline structure.
• ISA Variant: Targets the RV64GC variant, with the silicon measurement based on the RV64IMC configuration.
• Fabrication Process: GlobalFoundries 22 FDX (22nm Fully Depleted Silicon On Insulator) technology.
• Measured Overhead Factors: The analysis focused on the energy interplay of critical features required for application-class execution, including virtual memory support, caches, and multiple modes of privileged operation.
• Methodology: Analysis based on detailed power and efficiency data derived from actual silicon measurements combined with calibrated simulation.

Implications

• RISC-V Maturity for Applications: This work proves that open-source RISC-V designs can achieve the necessary performance (1.7 GHz) and efficiency targets required for running complex application environments like Linux, challenging established proprietary ISAs in the mid-range market.
• FDSOI Validation: The successful implementation in 22nm FDSOI validates this low-power, high-performance process technology as suitable and efficient for application-class RISC-V cores.
• Guidance for Core Developers: By quantifying the energy tax of features like virtual memory, the paper provides crucial data points for designers aiming to create truly energy-efficient, Linux-capable RISC-V CPUs.
• Future Efficiency Path: The conclusion strongly advocates for RISC-V’s flexibility, suggesting that simple cores coupled with custom, critical instruction extensions (like packed SIMD) represent the most effective path toward superior compute energy efficiency, leveraging the ISA's inherent customizability.