The BlackParrot BedRock Cache Coherence System
Abstract
This paper presents BP-BedRock, an open-source, directory-based MOESIF cache coherence system implemented within the BlackParrot 64-bit RISC-V multicore processor. The system notably includes both a fixed-function FSM and a microcode programmable coherence engine, validated in 8-core configurations and silicon using a 12nm FinFET process. The programmable controller achieves performance within 1% of the fixed FSM while adding only a 4% increase in ASIC die area, demonstrating high flexibility with minimal overhead.
Report
Key Highlights
- Open-Source Coherence: BP-BedRock is an open-source cache coherence protocol designed for the BlackParrot 64-bit RISC-V multicore processor.
- Dual Engine Design: The system features two distinct coherence protocol engines: a traditional Finite State Machine (FSM) controller and a highly flexible microcode programmable controller.
- Near-Parity Performance: The programmable engine achieves high efficiency, delivering performance within 1% (average) of the fixed-function FSM controller, validating that programmability does not inherently sacrifice speed.
- Low Overhead: The area increase attributed to the programmable coherence engine is minimal, calculated at only 4% in an ASIC process.
- Industrial Validation: The BP-BedRock system has been rigorously validated in silicon using a GlobalFoundries 12nm FinFET process and successfully run Linux and standard off-the-shelf benchmarks (Splash-3) on 8-core FPGA implementations.
Technical Details
| Feature | Specification/Detail |
|---|---|
| Target System | BlackParrot 64-bit RISC-V multicore processor |
| Protocol | Directory-based MOESIF (Modified, Owned, Exclusive, Shared, Invalid, Forward) BedRock protocol |
| Coherence Engines | Fixed-function FSM engine and Microcode Programmable engine |
| Special Features | Supports coherent uncacheable access and L1-based atomic Read-Modify-Write (RMW) operations |
| Worst-Case Performance | Programmable controller performs within 2.3% of the FSM controller |
| ASIC Implementation | GlobalFoundries 12nm FinFET process; programmable engine increases die area by 4% |
| FPGA Implementation | 8-core configuration; programmable engine increases logic utilization by 6.3% plus one additional Block RAM per core |
Implications
- Maturity of Open RISC-V IP: BP-BedRock offers a highly validated, industrial-strength, open-source coherence solution, further maturing the ecosystem necessary for complex RISC-V multicore designs.
- Architectural Flexibility: The introduction of a programmable coherence controller allows designers to easily adapt the cache coherence policy, potentially enabling rapid prototyping of new memory models or optimization for specific workloads without needing complex hardware redesigns.
- High Performance Programmability: Demonstrating that a programmable coherence controller can maintain near-fixed-function performance (within 1%) while drastically improving flexibility is a significant step toward future high-performance, adaptable architectures.
- Enabling Advanced Designs: Validation in a modern 12nm FinFET process confirms the design's viability for high-performance computing and complex chip tape-outs, lowering the barrier for entry for companies utilizing the BlackParrot framework.
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