The BaseJump Manycore Accelerator Network

Abstract

The BaseJump Manycore Accelerator Network is an open-source, mesh-based On-Chip-Network (OCN) developed using over 20 years of manycore architecture expertise. This scalable network served as the communication backbone for the 16nm 511-core RISC-V compatible Celerity chip, enabling a 496-core manycore cluster to run at 1 GHz. The paper details the network's protocols and interfaces, providing source code examples to facilitate integration and use by the broader open-source community.

Report

The BaseJump Manycore Accelerator Network Report

Key Highlights

• Open Source Network: BaseJump is an openly available, mesh-based On-Chip-Network (OCN) solution.
• Proven Pedigree: The design leverages 20+ years of expertise from the Bespoke Silicon Group in manycore architectures.
• High-Core Implementation: It successfully forms the basis of the 511-core RISC-V compatible Celerity chip, manufactured on a 16nm node.
• Performance Verification: The network supports a 496-core manycore cluster operating at 1 GHz.
• Community Focus: The accompanying documentation aims to explain the protocols and interfaces to encourage integration by open-source designers.

Technical Details

• Architecture: Mesh-based On-Chip-Network (OCN).
• Flagship Deployment: Celerity chip (16nm process).
• Celerity Configuration: Includes a 496-core RISC-V manycore section clocked at 1 GHz, alongside a 10-core always-on low voltage complex, totaling 511 functional cores.
• Legacy Deployment: Used in the 180nm BSG Ten chip.
• Advanced Connectivity: The implementation in the 180nm BSG Ten chip demonstrated the mesh extending over off-chip links to interface with an external FPGA.
• Deliverables: The paper explicitly mentions explaining the ideas, protocols, interfaces, and providing example source code for integration.

Implications

• Democratization of Manycore Design: By open-sourcing a validated, high-performance OCN, BaseJump significantly lowers the barrier to entry for sophisticated manycore acceleration research and development within the RISC-V ecosystem.
• Scalability for RISC-V Accelerators: The successful deployment on a cutting-edge 16nm process, supporting hundreds of cores at 1 GHz, validates RISC-V's viability for demanding applications like HPC and large-scale AI acceleration, where scalable interconnects are crucial.
• Industry Validation: The network brings expert, industry-level design principles directly to the academic and hobbyist community, accelerating the maturity of open-source hardware components necessary for building complete system-on-chips (SoCs).