The Accuracy and Efficiency of Posit Arithmetic

Abstract

This paper evaluates the accuracy and efficiency of posit arithmetic against traditional IEEE 754 FP32 by implementing a custom Posit Arithmetic Unit (POSAR) integrated into a RISC-V Rocket Chip core. While 32-bit posit offers better accuracy and minor execution speedup (up to 2%) in NPB, it requires 30% more FPGA resources than the standard FPU. Crucially, 16-bit posit provided the best trade-off for machine learning applications, achieving FP32 accuracy on a Cifar-10 CNN with a notable 18% execution speedup.

Report

Key Highlights

• Custom Unit: A Posit Arithmetic Unit (PAU), named POSAR, was designed and implemented with flexible bit-sizing capabilities.
• 32-bit Posit Performance: For NAS Parallel Benchmarks (NPB), 32-bit posit achieved better accuracy than FP32 and improved execution speed by up to 2%.
• Resource Overhead: Despite performance gains, the 32-bit POSAR required 30% more FPGA resources compared to the IEEE 754-based Floating Point Unit (FPU).
• 16-bit ML Efficiency: 16-bit posit proved optimal for machine learning (ML), matching FP32's Top-1 accuracy on a Cifar-10 CNN while providing an 18% speedup.
• Low Precision Warning: 8-bit posits were found unsuitable for replacing FP32 in classic ML algorithms due to significant accuracy loss leading to erroneous results.

Technical Details

• Architecture Tested: The evaluation used the custom-designed POSAR integrated directly into a RISC-V Rocket Chip core.
• Comparison Target: The POSAR performance was contrasted against the standard IEEE 754 Floating Point Unit (FPU) within the Rocket Chip.
• Posit Flexibility: POSAR supports variable bit-sized arithmetic, enabling tests across 8-bit, 16-bit, and 32-bit posits to assess trade-offs between chip area, accuracy, and speed.
• Benchmark Suite: The analysis utilized a wide range of benchmarks, including mathematical computations, machine learning kernels, NAS Parallel Benchmarks (NPB), and image classification (Cifar-10 CNN).

Implications

• RISC-V Specialization: This work validates the integration and viability of specialized arithmetic formats like posit within the open RISC-V ecosystem, particularly using the popular Rocket Chip framework.
• AI/ML Acceleration: The significant speedup (18%) demonstrated by 16-bit posits for CNNs, while maintaining FP32 accuracy, strongly suggests that posit arithmetic is a superior candidate for energy-efficient, reduced-precision AI accelerators over standard formats.
• Hardware Design Trade-offs: The results quantify the cost (30% area increase for 32-bit) versus the benefit of posit, guiding architects to focus on precision levels (16-bit) where the efficiency gains outweigh the resource overhead.
• Future Floating Point Standard: By showing tangible accuracy and performance improvements in specific workloads, the paper adds weight to the argument for considering posit arithmetic as a competitive, and sometimes superior, alternative to IEEE 754, particularly in domains like HPC and deep learning.