Teaching Experiences using the RVfpga Package

Abstract

The RVfpga course provides a robust, hands-on introduction to computer architecture using the RISC-V instruction set and FPGA technology. This paper details various successful teaching experiences, demonstrating its utility across undergraduate and graduate curricula, including integration into MOOCs and workshops. The package utilizes real RISC-V cores, specifically the ChipsAlliance-hosted VeeR EH1 and EL2, aligning with current computing curriculum guidelines.

Report

Key Highlights

• Free Educational Resource: The RVfpga package offers detailed course materials, labs, and setup guides available for free through the Imagination University Programme website.
• Hands-on RISC-V Experience: The course provides practical experience by implementing and working with real, industrial-grade RISC-V cores on FPGA hardware.
• Wide Deployment: RVfpga has been successfully integrated into multiple educational formats, including bachelor/master degree courses, final student projects, microcredentials, adaptation into an edX MOOC, and international hands-on workshops.
• Curriculum Alignment: The course materials are assessed and shown to match the latest IEEE/ACM/AAAI computing curriculum guidelines.

Technical Details

• Instruction Set Architecture (ISA): RISC-V.
• Hardware Platform: FPGA technology is used as the primary implementation and experimental platform.
• Specific Cores: The course uses the VeeR EH1 and the VeeR EL2 RISC-V cores.
• Core Ownership: These cores were initially developed by Western Digital and are now hosted and maintained by ChipsAlliance.
• Content Scope: The paper includes a comparison of RVfpga materials against the strengths and weaknesses of similar existing computer architecture courses.

Implications

• Standardization of RISC-V Education: RVfpga provides a high-quality, practical, and scalable curriculum, helping to standardize how computer architecture and processor design are taught globally.
• Workforce Development: By giving students hands-on experience with industrial-grade cores (VeeR series) and FPGA implementation, the course actively develops the practical engineering skills necessary to expand the RISC-V developer ecosystem.
• Accessibility and Outreach: Adaptation into a MOOC (edX) and global workshops ensures that advanced RISC-V and FPGA knowledge is accessible to a broad, non-traditional student audience, accelerating the adoption curve of the open ISA.