Supporting Custom Instructions with the LLVM Compiler for RISC-V Processor

Abstract

This study analyzes the process of integrating custom hardware instructions into the LLVM compiler backend for RISC-V processors, driven by the need for high-performance hardware accelerators. The authors delineate the required compiler modifications into two parts: basic Assembler support and scalable pattern matching support. They conclude that supporting complex instruction patterns often necessitates using higher-level transformations, such as at the Intermediate Representation (IR) level, thereby emphasizing that instruction design must equally consider compiler maintainability.

Report

Key Highlights

• Provides a detailed analysis of the LLVM compiler and its RISC-V backend regarding the integration of custom instructions.
• Identifies two crucial stages for adding custom compiler support: trivial Assembler support and critical, scalable pattern matching support.
• Highlights that effective custom instruction design requires consideration of both the hardware design space and the software (compiler) design space.
• Emphasizes that omitting pattern matching forces developers to use non-scalable inline assembly for custom instruction usage.
• Suggests using RISC-V standard extensions as exemplary guidance for designers creating new instructions.

Technical Details

• Target Architecture/Compiler: Focuses on the LLVM compiler infrastructure and its RISC-V target backend.
• Custom Instruction Support Phases: The process is formally split into Assembler support and pattern matching support.
• Complexity Management: The choice of where to implement pattern matching depends heavily on the instruction's complexity.
• Preferred Optimization Stage: For complex patterns, the study recommends making modifications at higher-level transformations (specifically the IR level) rather than solely relying on the Instruction Selection phase, due to improved maintainability.

Implications

• Enabling RISC-V Customization: Directly supports the core philosophy of RISC-V by providing a practical and scalable path for hardware designers to incorporate their domain-specific accelerators.
• Compiler-Aware Hardware Design: Establishes a crucial feedback loop where compiler constraints and modification difficulty serve as a litmus test for the quality and design of the custom instruction itself.
• Improved Developer Experience: By focusing on robust pattern matching, the methodology allows conventional software to efficiently utilize accelerators, moving away from error-prone and non-portable manual inline assembly, thereby accelerating the adoption of new RISC-V extensions.