Static Hardware Partitioning on RISC-V -- Shortcomings, Limitations, and Prospects

Abstract

This paper investigates the viability of static hardware partitioning (SHP) on multi-core RISC-V processors essential for consolidating mixed-criticality and real-time embedded workloads while ensuring freedom from interference. The authors identify significant shortcomings in current RISC-V specifications and implementations, particularly regarding interrupt handling, which necessitate intervention from superordinate control structures. These limitations prevent the realization of true zero-overhead partitioning, providing a necessary basis for future architectural extensions to satisfy robust real-time and safety requirements.

Report

Static Hardware Partitioning on RISC-V: Analysis Report

Key Highlights

• Static Hardware Partitioning (SHP) is investigated as a method to consolidate and isolate mixed-criticality workloads on multi-core embedded processors.
• The central goal of effective SHP is achieving freedom from interference with zero overhead, which means zero interventions from superordinate control structures.
• Current standard hardware systems, including contemporary RISC-V implementations, lack the required capabilities to achieve zero-intervention partitioning.
• The authors identified numerous design-level issues in the RISC-V specification that are adverse to SHP, most notably concerning the handling of interrupts.
• Micro-benchmark measurements were used to discuss and validate the performance implications of these findings.

Technical Details

• Architectural Pattern: Static Hardware Partitioning, exploiting contemporary virtualization mechanisms for isolation.
• Isolation Criteria: Achieving temporal and spatial isolation, maintaining real-time capabilities, and avoiding device sharing.
• Target Specification: The customizable and configurable nature of the RISC-V Instruction Set Architecture (ISA) is cited as a prospect for implementing swift hardware modifications.
• Specific Limitations: The core issues identified stem from how current RISC-V systems handle critical resources (like interrupts) which currently force interventions from high-level control structures (e.g., hypervisors), contradicting the goal of zero-overhead isolation.

Implications

• Safety and Real-Time Performance: The necessity for interventions by superordinate control structures introduces overhead and potential interference, fundamentally challenging the ability of current RISC-V implementations to meet stringent safety (e.g., ISO 26262) and real-time requirements.
• Roadmap for RISC-V: The paper provides concrete findings that can guide future development and standardization of the RISC-V architecture. These necessary extensions must focus on robust, hardware-enforced isolation primitives, especially concerning interrupt management.
• Ecosystem Maturity: While RISC-V is gaining traction in embedded systems, the study highlights that specific architectural gaps must be closed before it can fully satisfy the requirements of high-integrity, mixed-criticality domains where guaranteed freedom from interference is mandatory.