SSRESF: Sensitivity-aware Single-particle Radiation Effects Simulation Framework in SoC Platforms based on SVM Algorithm

Abstract

This paper introduces SSRESF, a Sensitivity-aware Single-particle Radiation Effects Simulation Framework designed to overcome the limitations of traditional radiation testing in large-scale System-on-Chip (SoC) designs. SSRESF utilizes the Support Vector Machine (SVM) algorithm to quickly identify and classify sensitive circuit nodes, streamlining soft error analysis across the entire software stack. Experimental results focusing on RISC-V architecture demonstrate high efficacy, achieving 94.58% accuracy while providing up to a 12.78X speed-up over existing methods.

Report

Key Highlights

• Novel Framework: SSRESF (Sensitivity-aware Single-particle Radiation Effects Simulation Framework) is introduced to address radiation design risks in large-scale integrated circuits (ICs).
• Performance Breakthrough: The simulation achieves a maximum speed-up of 12.78X while maintaining high accuracy (94.58%).
• Sensitivity-Aware: The framework focuses on the fast finding and classification of sensitive circuit nodes using machine learning.
• Broad Scope: The methodology automates soft error analysis across the entire software stack and was validated on core components, buses, and memory systems.
• Data Generation: The study culminated in the establishment of critical databases for Single Event Upsets (SEU) and Single Event Transients (SET).

Technical Details

• Target Platform: System-on-Chip (SoC) architectures.
• Core Methodology: The framework is built upon the Support Vector Machine (SVM) algorithm to efficiently identify radiation-sensitive circuit nodes, bypassing the need for extensive iterative physical experiments.
• Architecture Tested: The practical experiments specifically focused on the RISC-V instruction set architecture (ISA) and its associated platform components.
• Error Types Cataloged: The simulation generated databases detailing both SEU (errors that flip a state in memory/register) and SET (transient voltage pulses that can cause soft errors).

Implications

• Accelerated Hardening Process: The 12.78X speed-up fundamentally transforms the radiation-hardening design flow, making the verification of large, complex SoCs economically viable and significantly faster than traditional physical or time-intensive simulation approaches.
• RISC-V Ecosystem Reliability: By specifically targeting the RISC-V architecture, this research provides vital tools necessary for establishing reliability standards and developing radiation-tolerant RISC-V chips for applications in aerospace, defense, and high-altitude environments.
• AI/ML in Hardware Design: This work demonstrates a powerful application of machine learning (SVM) in complex hardware verification and fault analysis, setting a precedent for integrating AI algorithms into future Computer-Aided Design (CAD) tools for resilience modeling.