Spatzformer: An Efficient Reconfigurable Dual-Core RISC-V V Cluster for Mixed Scalar-Vector Workloads

Abstract

Spatzformer is the first reconfigurable dual-core RISC-V V (RVV) cluster designed to overcome the efficiency limitations of multi-core vector processors when facing mixed scalar-vector workloads. It operates in two modes—split mode for concurrent vector tasks and merge mode where one scalar core controls both vector units—to maximize resource utilization for non-vectorizable control tasks. Implemented in 12-nm technology, the merge mode achieves up to 1.8x acceleration in mixed kernels with a negligible area overhead of only 1.4% and sustained 1.2 GHz frequency.

Report

Spatzformer Analysis Report

Key Highlights

• Novel Reconfiguration: Spatzformer is the first reconfigurable dual-core RISC-V V (RVV) architecture, built upon open-source Snitch scalar cores and Spatz vector units.
• Dual Operating Modes: It supports a flexible execution model with Split Mode (concurrent dual-core vector processing) and Merge Mode (one scalar core driving two vector units while the other scalar core handles control tasks).
• Performance Gain: The Merge Mode accelerates mixed scalar-vector kernels by up to 1.8x compared to the standard split mode.
• Minimal Overhead: The added reconfigurability features resulted in a negligible area impact (+1.4%) and maintained the maximum clock frequency of 1.2 GHz.
• Synchronization Improvement: It accelerates vector kernels requiring fine-grained synchronization (like FFT) by up to 20% compared to the non-reconfigurable baseline.

Technical Details

• Architecture Base: Uses a baseline dual-core cluster featuring open-source Snitch scalar cores.
• Vector Units: Augmented with compact Spatz vector units, implementing the RISC-V Vector (RVV) extension.
• Merge Mode Functionality: In Merge Mode, the two available vector units are logically unified and driven by a single scalar core, dedicating the second scalar core to necessary sequential or control flow tasks.
• Technology Implementation: Implemented and characterized in a 12-nm technology node.
• Frequency and Voltage: Achieved a maximum operating frequency of 1.2 GHz (TT, 0.8V, 25C).
• Efficiency Metrics: The worst-case energy efficiency drop due to reconfigurability was limited to only 7% relative to the non-reconfigurable baseline architecture.

Implications

• Enhanced Heterogeneous Processing: Spatzformer successfully addresses the inherent challenge of mixed workloads (combining intense vector computation and sequential control tasks) on traditional vector processors, making it highly suitable for modern computing demands like AI inference.
• Advancement of Open-Source RISC-V Vector Ecosystem: By building on open-source components (Snitch/Spatz) and demonstrating high efficiency, the work provides a high-performance, verifiable reference architecture for future RISC-V vector cluster designs.
• Area-Efficient Flexibility: The demonstration that significant architectural flexibility (up to 1.8x speedup) can be achieved with minimal hardware cost (+1.4% area) sets a strong precedent for creating specialized, highly efficient custom accelerators within the RISC-V domain without sacrificing clock speed or power.
• Improved Synchronization Handling: The specific acceleration for fine-grained synchronization tasks (like FFT) suggests that this architecture is highly effective for signal processing and scientific computing applications that require tightly coupled multi-core operation.