Sparse Stream Semantic Registers: A Lightweight ISA Extension Accelerating General Sparse Linear Algebra

Abstract

This paper introduces Sparse Stream Semantic Registers (SSSR), a lightweight ISA extension for RISC-V designed to accelerate general sparse linear algebra by efficiently handling both one- and two-sided operand sparsity. SSSR accelerates fundamental sparse operations—streaming indirection, intersection, and union—across formats like CSR and CSF. This approach yields dramatic performance benefits, achieving speedups up to 9.8x and 3.0x greater energy efficiency on multi-core clusters, all while utilizing a minimal hardware footprint of just 1.8% area increase.

Report

Key Highlights

• Key Innovation: The introduction of Sparse Stream Semantic Registers (SSSR), a lightweight extension to an existing RISC-V memory-streaming ISA.
• Performance Gains (Single Core): Achieves speedups up to 7.0x (sparse-dense multiply), 7.7x (sparse-sparse multiply), and 9.8x (sparse-sparse addition).
• Cluster Efficiency: On an eight-core cluster, sparse matrix-vector multiplication (MVM) is accelerated by up to 5.9x and demonstrates up to 3.0x greater energy efficiency.
• Hardware Footprint: Requires only a minimal 1.8% increase in area to the compute cluster.
• FPU Utilization: Achieves peak FPU utilizations of up to 80% on sparse-dense problems, and 9.9x higher peak utilization compared to recent highly optimized CPU sparse data structures.

Technical Details

• Scope: Designed to efficiently accelerate both one-sided and two-sided operand sparsity.
• Supported Formats: The extension is optimized for widespread sparse tensor formats, including Compressed Sparse Row (CSR) and Compressed Sparse Fiber (CSF).
• Accelerated Operations: The ISA extension specifically targets and accelerates the underlying complex operations inherent to sparse linear algebra: streaming indirection, intersection, and union.
• Flexibility: The design offers high flexibility concerning data representation, the degree of sparsity, and the required dataflow.
• Comparison Basis: Performance metrics were measured against an optimized RISC-V baseline and compared favorably against recent specialized CPU, GPU, and accelerator approaches.

Implications

• Standardizing Sparse Compute: By offering high performance for general sparse linear algebra with a minimal hardware footprint, SSSR provides a viable path to integrating efficient sparse processing capabilities directly into mainstream RISC-V cores.
• Ecosystem Competitiveness: The extension enables RISC-V cores to achieve competitive, and often superior, performance and energy efficiency metrics (up to 9.9x FPU utilization improvement over CPU structures) relative to highly specialized or resource-intensive GPU and custom accelerator solutions.
• Broad Application: The accelerated operations are foundational for many compute-intensive fields beyond standard linear algebra, including stencil codes and critical graph pattern matching algorithms, expanding the utility of RISC-V in AI/ML and scientific computing.
• Cost-Benefit Ratio: The minuscule 1.8% area overhead makes this ISA extension extremely cost-effective, suggesting its rapid adoption could accelerate the deployment of high-performance sparse computing capabilities.